/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Marvell 88E6xxx PHY access
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*
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* Copyright (c) 2008 Marvell Semiconductor
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*
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* Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
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*/
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#ifndef _MV88E6XXX_PHY_H
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#define _MV88E6XXX_PHY_H
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#define MV88E6XXX_PHY_PAGE 0x16
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#define MV88E6XXX_PHY_PAGE_COPPER 0x00
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/* PHY Registers accesses implementations */
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int mv88e6165_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
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int addr, int reg, u16 *val);
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int mv88e6165_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
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int addr, int reg, u16 val);
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int mv88e6185_phy_ppu_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
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int addr, int reg, u16 *val);
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int mv88e6185_phy_ppu_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
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int addr, int reg, u16 val);
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/* Generic PHY operations */
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int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
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int reg, u16 *val);
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int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
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int reg, u16 val);
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int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
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u8 page, int reg, u16 *val);
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int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
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u8 page, int reg, u16 val);
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void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip);
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void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip);
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int mv88e6xxx_phy_setup(struct mv88e6xxx_chip *chip);
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#endif /*_MV88E6XXX_PHY_H */
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