/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. */
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#ifndef _RKISP_ISPP_H
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#define _RKISP_ISPP_H
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#include <linux/platform_device.h>
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#include <media/v4l2-subdev.h>
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#include <media/videobuf2-v4l2.h>
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#include <linux/rk-isp1-config.h>
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#include <linux/rk-ispp-config.h>
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#define RKISP_BUF_MAX 2
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#define RKISPP_BUF_MAX 2
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#define RKISP_ISPP_BUF_MAX (RKISP_BUF_MAX + RKISPP_BUF_MAX + (2 * (DEV_MAX - 1)))
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#define RKISP_ISPP_REGBUF_NUM RKISPP_BUF_POOL_MAX
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#define RKISP_ISP_SW_REG_SIZE 0x6000
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#define RKISP_ISP_SW_MAX_SIZE (RKISP_ISP_SW_REG_SIZE * 2)
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#define RKISP_ISPP_SW_REG_SIZE 0x0d00
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#define RKISP_ISPP_SW_MAX_SIZE (RKISP_ISPP_SW_REG_SIZE * 2)
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#define RKISP_ISPP_CMD_SET_MODE \
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_IOW('V', BASE_VIDIOC_PRIVATE + 0, struct rkisp_ispp_mode)
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#define RKISP_ISPP_CMD_SET_FMT \
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_IOW('V', BASE_VIDIOC_PRIVATE + 1, struct max_input)
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#define RKISP_ISPP_CMD_REQUEST_REGBUF \
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_IOW('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_ispp_reg *)
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#define RKISP_ISPP_CMD_GET_REG_WITHSTREAM \
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_IOW('V', BASE_VIDIOC_PRIVATE + 3, bool)
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enum frame_end_state {
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FRAME_INIT,
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FRAME_IRQ,
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FRAME_WORK,
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};
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enum rkisp_ispp_dev {
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DEV_ID0 = 0,
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DEV_ID1,
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DEV_ID2,
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DEV_ID3,
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DEV_MAX,
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};
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enum rkisp_ispp_sw_reg {
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SW_REG_CACHE = 0xffffffff,
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SW_REG_CACHE_SYNC = 0xeeeeeeee,
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};
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enum rkisp_ispp_buf_group {
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GROUP_BUF_PIC = 0,
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GROUP_BUF_GAIN,
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GROUP_BUF_MAX,
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};
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enum rkisp_ispp_work_mode {
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ISP_ISPP_FBC = BIT(0),
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ISP_ISPP_422 = BIT(1),
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ISP_ISPP_QUICK = BIT(2),
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ISP_ISPP_INIT_FAIL = BIT(7),
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};
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enum rkisp_ispp_reg_stat {
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ISP_ISPP_FREE = 0,
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ISP_ISPP_INUSE,
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};
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struct frame_debug_info {
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u64 timestamp;
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u32 interval;
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u32 delay;
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u32 id;
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u32 frameloss;
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};
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struct max_input {
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u32 w;
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u32 h;
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u32 fps;
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bool is_fix;
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};
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struct rkisp_ispp_mode {
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u8 work_mode;
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u8 buf_num;
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};
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struct rkisp_ispp_reg {
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enum rkisp_ispp_reg_stat stat;
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u32 dev_id;
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u32 frame_id;
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u32 reg_size;
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s32 isp_offset[ISP2X_ID_MAX];
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s32 ispp_offset[ISPP_ID_MAX];
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u32 isp_size[ISP2X_ID_MAX];
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u32 isp_stats_size[ISP2X_ID_MAX];
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u32 ispp_size[ISPP_ID_MAX];
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u64 sof_timestamp;
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u64 frame_timestamp;
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struct sensor_exposure_cfg exposure;
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u8 reg[RKISP_ISP_SW_REG_SIZE + RKISP_ISPP_SW_REG_SIZE];
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};
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struct rkisp_ispp_buf {
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struct list_head list;
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struct dma_buf *dbuf[GROUP_BUF_MAX];
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int dfd[GROUP_BUF_MAX];
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u32 didx[GROUP_BUF_MAX];
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/* timestamp in ns */
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u64 frame_timestamp;
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u32 frame_id;
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u32 index;
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bool is_isp;
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bool is_move_judge;
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u32 buf_idx;
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u32 gain_dmaidx;
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u32 mfbc_dmaidx;
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u32 gain_size;
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u32 mfbc_size;
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void *priv;
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};
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int __init rkispp_hw_drv_init(void);
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#if IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V20) || IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_ISP_VERSION_V30)
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void rkisp_get_bridge_sd(struct platform_device *dev,
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struct v4l2_subdev **sd);
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#else
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static inline void rkisp_get_bridge_sd(struct platform_device *dev,
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struct v4l2_subdev **sd)
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{
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*sd = NULL;
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}
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#endif
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#endif
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