/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2021 Rockchip Electronics Co. Ltd.
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*
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* Author: Shunqing Chen <csq@rock-chips.com>
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*/
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#ifndef __RK_HDMIRX_CEC_H__
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#define __RK_HDMIRX_CEC_H__
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struct rk_hdmirx_dev;
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struct hdmirx_cec_ops {
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void (*write)(struct rk_hdmirx_dev *hdmirx_dev, int reg, u32 val);
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u32 (*read)(struct rk_hdmirx_dev *hdmirx_dev, int reg);
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void (*enable)(struct rk_hdmirx_dev *hdmirx);
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void (*disable)(struct rk_hdmirx_dev *hdmirx);
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};
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struct hdmirx_cec_data {
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struct rk_hdmirx_dev *hdmirx;
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const struct hdmirx_cec_ops *ops;
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struct device *dev;
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int irq;
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u8 *edid;
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};
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struct hdmirx_cec {
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struct rk_hdmirx_dev *hdmirx;
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struct device *dev;
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const struct hdmirx_cec_ops *ops;
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u32 addresses;
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struct cec_adapter *adap;
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struct cec_msg rx_msg;
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unsigned int tx_status;
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bool tx_done;
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bool rx_done;
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struct cec_notifier *notify;
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int irq;
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struct edid *edid;
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};
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struct hdmirx_cec *rk_hdmirx_cec_register(struct hdmirx_cec_data *data);
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void rk_hdmirx_cec_unregister(struct hdmirx_cec *cec);
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#endif /* __DW_HDMI_RX_CEC_H__ */
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