// SPDX-License-Identifier: GPL-2.0
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/{
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dpe: dpe@E8600000 {
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compatible = "hisilicon,hi3660-dpe";
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status = "ok";
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reg = <0x0 0xE8600000 0x0 0x80000>,
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<0x0 0xFFF35000 0 0x1000>,
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<0x0 0xFFF0A000 0 0x1000>,
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<0x0 0xFFF31000 0 0x1000>,
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<0x0 0xE86C0000 0 0x10000>;
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interrupts = <0 245 4>;
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clocks = <&crg_ctrl HI3660_ACLK_GATE_DSS>,
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<&crg_ctrl HI3660_PCLK_GATE_DSS>,
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<&crg_ctrl HI3660_CLK_GATE_EDC0>,
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<&crg_ctrl HI3660_CLK_GATE_LDI0>,
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<&crg_ctrl HI3660_CLK_GATE_LDI1>,
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<&sctrl HI3660_CLK_GATE_DSS_AXI_MM>,
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<&sctrl HI3660_PCLK_GATE_MMBUF>;
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clock-names = "aclk_dss",
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"pclk_dss",
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"clk_edc0",
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"clk_ldi0",
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"clk_ldi1",
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"clk_dss_axi_mm",
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"pclk_mmbuf";
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dma-coherent;
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port {
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dpe_out: endpoint {
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remote-endpoint = <&dsi_in>;
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};
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};
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iommu_info {
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start-addr = <0x8000>;
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size = <0xbfff8000>;
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};
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};
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dsi: dsi@E8601000 {
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compatible = "hisilicon,hi3660-dsi";
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status = "ok";
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reg = <0 0xE8601000 0 0x7F000>,
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<0 0xFFF35000 0 0x1000>;
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clocks = <&crg_ctrl HI3660_CLK_GATE_TXDPHY0_REF>,
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<&crg_ctrl HI3660_CLK_GATE_TXDPHY1_REF>,
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<&crg_ctrl HI3660_CLK_GATE_TXDPHY0_CFG>,
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<&crg_ctrl HI3660_CLK_GATE_TXDPHY1_CFG>,
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<&crg_ctrl HI3660_PCLK_GATE_DSI0>,
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<&crg_ctrl HI3660_PCLK_GATE_DSI1>;
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clock-names = "clk_txdphy0_ref",
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"clk_txdphy1_ref",
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"clk_txdphy0_cfg",
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"clk_txdphy1_cfg",
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"pclk_dsi0",
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"pclk_dsi1";
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#address-cells = <1>;
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#size-cells = <0>;
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mux-gpio = <&gpio2 4 0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi_in: endpoint {
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remote-endpoint = <&dpe_out>;
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};
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};
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port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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dsi_out0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&adv7533_in>;
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};
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};
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};
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};
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};
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