/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Tony Xie <tony.xie@rock-chips.com>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/memory.h>
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.data
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/*
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* this code will be copied from
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* ddr to sram for system resumeing.
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* so it is ".data section".
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*/
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.align 2
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ENTRY(rockchip_slp_cpu_resume)
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setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
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mrc p15, 0, r1, c0, c0, 5
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and r1, r1, #0xf
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cmp r1, #0
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/* olny cpu0 can continue to run, the others is halt here */
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beq cpu0run
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secondary_loop:
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wfe
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b secondary_loop
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cpu0run:
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ldr r3, rkpm_bootdata_l2ctlr_f
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cmp r3, #0
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beq sp_set
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ldr r3, rkpm_bootdata_l2ctlr
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mcr p15, 1, r3, c9, c0, 2
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sp_set:
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ldr sp, rkpm_bootdata_cpusp
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ldr r1, rkpm_bootdata_cpu_code
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bx r1
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ENDPROC(rockchip_slp_cpu_resume)
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/* Parameters filled in by the kernel */
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/* Flag for whether to restore L2CTLR on resume */
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.global rkpm_bootdata_l2ctlr_f
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rkpm_bootdata_l2ctlr_f:
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.long 0
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/* Saved L2CTLR to restore on resume */
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.global rkpm_bootdata_l2ctlr
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rkpm_bootdata_l2ctlr:
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.long 0
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/* CPU resume SP addr */
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.globl rkpm_bootdata_cpusp
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rkpm_bootdata_cpusp:
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.long 0
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/* CPU resume function (physical address) */
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.globl rkpm_bootdata_cpu_code
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rkpm_bootdata_cpu_code:
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.long 0
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ENTRY(rk3288_bootram_sz)
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.word . - rockchip_slp_cpu_resume
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