/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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*
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* (C) COPYRIGHT 2019-2021 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#ifndef _UAPI_KBASE_GPU_REGMAP_CSF_H_
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#define _UAPI_KBASE_GPU_REGMAP_CSF_H_
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#include <linux/types.h>
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#if !MALI_USE_CSF && defined(__KERNEL__)
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#error "Cannot be compiled with JM"
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#endif
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/* IPA control registers */
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#define IPA_CONTROL_BASE 0x40000
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#define IPA_CONTROL_REG(r) (IPA_CONTROL_BASE+(r))
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#define COMMAND 0x000 /* (WO) Command register */
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#define STATUS 0x004 /* (RO) Status register */
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#define TIMER 0x008 /* (RW) Timer control register */
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#define SELECT_CSHW_LO 0x010 /* (RW) Counter select for CS hardware, low word */
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#define SELECT_CSHW_HI 0x014 /* (RW) Counter select for CS hardware, high word */
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#define SELECT_MEMSYS_LO 0x018 /* (RW) Counter select for Memory system, low word */
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#define SELECT_MEMSYS_HI 0x01C /* (RW) Counter select for Memory system, high word */
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#define SELECT_TILER_LO 0x020 /* (RW) Counter select for Tiler cores, low word */
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#define SELECT_TILER_HI 0x024 /* (RW) Counter select for Tiler cores, high word */
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#define SELECT_SHADER_LO 0x028 /* (RW) Counter select for Shader cores, low word */
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#define SELECT_SHADER_HI 0x02C /* (RW) Counter select for Shader cores, high word */
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/* Accumulated counter values for CS hardware */
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#define VALUE_CSHW_BASE 0x100
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#define VALUE_CSHW_REG_LO(n) (VALUE_CSHW_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */
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#define VALUE_CSHW_REG_HI(n) (VALUE_CSHW_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
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/* Accumulated counter values for memory system */
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#define VALUE_MEMSYS_BASE 0x140
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#define VALUE_MEMSYS_REG_LO(n) (VALUE_MEMSYS_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */
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#define VALUE_MEMSYS_REG_HI(n) (VALUE_MEMSYS_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
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#define VALUE_TILER_BASE 0x180
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#define VALUE_TILER_REG_LO(n) (VALUE_TILER_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */
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#define VALUE_TILER_REG_HI(n) (VALUE_TILER_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
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#define VALUE_SHADER_BASE 0x1C0
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#define VALUE_SHADER_REG_LO(n) (VALUE_SHADER_BASE + ((n) << 3)) /* (RO) Counter value #n, low word */
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#define VALUE_SHADER_REG_HI(n) (VALUE_SHADER_BASE + ((n) << 3) + 4) /* (RO) Counter value #n, high word */
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#include "../../csf/mali_gpu_csf_control_registers.h"
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/* Set to implementation defined, outer caching */
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#define AS_MEMATTR_AARCH64_OUTER_IMPL_DEF 0x88ull
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/* Set to write back memory, outer caching */
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#define AS_MEMATTR_AARCH64_OUTER_WA 0x8Dull
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/* Set to inner non-cacheable, outer-non-cacheable
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* Setting defined by the alloc bits is ignored, but set to a valid encoding:
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* - no-alloc on read
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* - no alloc on write
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*/
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#define AS_MEMATTR_AARCH64_NON_CACHEABLE 0x4Cull
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/* Set to shared memory, that is inner cacheable on ACE and inner or outer
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* shared, otherwise inner non-cacheable.
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* Outer cacheable if inner or outer shared, otherwise outer non-cacheable.
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*/
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#define AS_MEMATTR_AARCH64_SHARED 0x8ull
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/* Symbols for default MEMATTR to use
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* Default is - HW implementation defined caching
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*/
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#define AS_MEMATTR_INDEX_DEFAULT 0
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#define AS_MEMATTR_INDEX_DEFAULT_ACE 3
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/* HW implementation defined caching */
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#define AS_MEMATTR_INDEX_IMPL_DEF_CACHE_POLICY 0
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/* Force cache on */
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#define AS_MEMATTR_INDEX_FORCE_TO_CACHE_ALL 1
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/* Write-alloc */
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#define AS_MEMATTR_INDEX_WRITE_ALLOC 2
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/* Outer coherent, inner implementation defined policy */
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#define AS_MEMATTR_INDEX_OUTER_IMPL_DEF 3
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/* Outer coherent, write alloc inner */
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#define AS_MEMATTR_INDEX_OUTER_WA 4
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/* Normal memory, inner non-cacheable, outer non-cacheable (ARMv8 mode only) */
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#define AS_MEMATTR_INDEX_NON_CACHEABLE 5
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/* Normal memory, shared between MCU and Host */
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#define AS_MEMATTR_INDEX_SHARED 6
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/* Configuration bits for the CSF. */
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#define CSF_CONFIG 0xF00
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/* CSF_CONFIG register */
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#define CSF_CONFIG_FORCE_COHERENCY_FEATURES_SHIFT 2
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/* GPU control registers */
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#define CORE_FEATURES 0x008 /* () Shader Core Features */
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#define MCU_CONTROL 0x700
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#define MCU_STATUS 0x704
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#define MCU_CNTRL_ENABLE (1 << 0)
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#define MCU_CNTRL_AUTO (1 << 1)
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#define MCU_CNTRL_DISABLE (0)
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#define MCU_STATUS_HALTED (1 << 1)
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#define PRFCNT_BASE_LO 0x060 /* (RW) Performance counter memory
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* region base address, low word
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*/
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#define PRFCNT_BASE_HI 0x064 /* (RW) Performance counter memory
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* region base address, high word
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*/
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#define PRFCNT_CONFIG 0x068 /* (RW) Performance counter
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* configuration
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*/
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#define PRFCNT_CSHW_EN 0x06C /* (RW) Performance counter
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* enable for CS Hardware
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*/
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#define PRFCNT_SHADER_EN 0x070 /* (RW) Performance counter enable
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* flags for shader cores
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*/
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#define PRFCNT_TILER_EN 0x074 /* (RW) Performance counter enable
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* flags for tiler
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*/
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#define PRFCNT_MMU_L2_EN 0x07C /* (RW) Performance counter enable
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* flags for MMU/L2 cache
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*/
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/* JOB IRQ flags */
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#define JOB_IRQ_GLOBAL_IF (1 << 31) /* Global interface interrupt received */
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/* GPU_COMMAND codes */
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#define GPU_COMMAND_CODE_NOP 0x00 /* No operation, nothing happens */
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#define GPU_COMMAND_CODE_RESET 0x01 /* Reset the GPU */
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#define GPU_COMMAND_CODE_PRFCNT 0x02 /* Clear or sample performance counters */
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#define GPU_COMMAND_CODE_TIME 0x03 /* Configure time sources */
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#define GPU_COMMAND_CODE_FLUSH_CACHES 0x04 /* Flush caches */
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#define GPU_COMMAND_CODE_SET_PROTECTED_MODE 0x05 /* Places the GPU in protected mode */
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#define GPU_COMMAND_CODE_FINISH_HALT 0x06 /* Halt CSF */
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#define GPU_COMMAND_CODE_CLEAR_FAULT 0x07 /* Clear GPU_FAULTSTATUS and GPU_FAULTADDRESS, TODX */
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/* GPU_COMMAND_RESET payloads */
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/* This will leave the state of active jobs UNDEFINED, but will leave the external bus in a defined and idle state.
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* Power domains will remain powered on.
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*/
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#define GPU_COMMAND_RESET_PAYLOAD_FAST_RESET 0x00
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/* This will leave the state of active CSs UNDEFINED, but will leave the external bus in a defined and
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* idle state.
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*/
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#define GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET 0x01
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/* This reset will leave the state of currently active streams UNDEFINED, will likely lose data, and may leave
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* the system bus in an inconsistent state. Use only as a last resort when nothing else works.
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*/
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#define GPU_COMMAND_RESET_PAYLOAD_HARD_RESET 0x02
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/* GPU_COMMAND_PRFCNT payloads */
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#define GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE 0x01 /* Sample performance counters */
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#define GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR 0x02 /* Clear performance counters */
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/* GPU_COMMAND_TIME payloads */
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#define GPU_COMMAND_TIME_DISABLE 0x00 /* Disable cycle counter */
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#define GPU_COMMAND_TIME_ENABLE 0x01 /* Enable cycle counter */
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/* GPU_COMMAND_FLUSH_CACHES payloads */
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#define GPU_COMMAND_FLUSH_PAYLOAD_NONE 0x00 /* No flush */
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#define GPU_COMMAND_FLUSH_PAYLOAD_CLEAN 0x01 /* Clean the caches */
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#define GPU_COMMAND_FLUSH_PAYLOAD_INVALIDATE 0x02 /* Invalidate the caches */
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#define GPU_COMMAND_FLUSH_PAYLOAD_CLEAN_INVALIDATE 0x03 /* Clean and invalidate the caches */
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/* GPU_COMMAND command + payload */
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#define GPU_COMMAND_CODE_PAYLOAD(opcode, payload) \
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((__u32)opcode | ((__u32)payload << 8))
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/* Final GPU_COMMAND form */
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/* No operation, nothing happens */
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#define GPU_COMMAND_NOP \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_NOP, 0)
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/* Stop all external bus interfaces, and then reset the entire GPU. */
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#define GPU_COMMAND_SOFT_RESET \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_SOFT_RESET)
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/* Immediately reset the entire GPU. */
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#define GPU_COMMAND_HARD_RESET \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_RESET, GPU_COMMAND_RESET_PAYLOAD_HARD_RESET)
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/* Clear all performance counters, setting them all to zero. */
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#define GPU_COMMAND_PRFCNT_CLEAR \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_CLEAR)
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/* Sample all performance counters, writing them out to memory */
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#define GPU_COMMAND_PRFCNT_SAMPLE \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_PRFCNT, GPU_COMMAND_PRFCNT_PAYLOAD_SAMPLE)
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/* Starts the cycle counter, and system timestamp propagation */
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#define GPU_COMMAND_CYCLE_COUNT_START \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_ENABLE)
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/* Stops the cycle counter, and system timestamp propagation */
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#define GPU_COMMAND_CYCLE_COUNT_STOP \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_TIME, GPU_COMMAND_TIME_DISABLE)
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/* Clean all caches */
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#define GPU_COMMAND_CLEAN_CACHES \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FLUSH_CACHES, GPU_COMMAND_FLUSH_PAYLOAD_CLEAN)
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/* Clean and invalidate all caches */
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#define GPU_COMMAND_CLEAN_INV_CACHES \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FLUSH_CACHES, GPU_COMMAND_FLUSH_PAYLOAD_CLEAN_INVALIDATE)
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/* Places the GPU in protected mode */
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#define GPU_COMMAND_SET_PROTECTED_MODE \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_SET_PROTECTED_MODE, 0)
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/* Halt CSF */
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#define GPU_COMMAND_FINISH_HALT \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_FINISH_HALT, 0)
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/* Clear GPU faults */
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#define GPU_COMMAND_CLEAR_FAULT \
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GPU_COMMAND_CODE_PAYLOAD(GPU_COMMAND_CODE_CLEAR_FAULT, 0)
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/* End Command Values */
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/* GPU_FAULTSTATUS register */
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#define GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT 0
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#define GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFFul)
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#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
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(((reg_val)&GPU_FAULTSTATUS_EXCEPTION_TYPE_MASK) \
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>> GPU_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
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#define GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT 8
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#define GPU_FAULTSTATUS_ACCESS_TYPE_MASK \
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(0x3ul << GPU_FAULTSTATUS_ACCESS_TYPE_SHIFT)
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#define GPU_FAULTSTATUS_ADDR_VALID_SHIFT 10
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#define GPU_FAULTSTATUS_ADDR_VALID_FLAG \
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(1ul << GPU_FAULTSTATUS_ADDR_VALID_SHIFT)
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#define GPU_FAULTSTATUS_JASID_VALID_SHIFT 11
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#define GPU_FAULTSTATUS_JASID_VALID_FLAG \
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(1ul << GPU_FAULTSTATUS_JASID_VALID_SHIFT)
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#define GPU_FAULTSTATUS_JASID_SHIFT 12
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#define GPU_FAULTSTATUS_JASID_MASK (0xF << GPU_FAULTSTATUS_JASID_SHIFT)
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#define GPU_FAULTSTATUS_JASID_GET(reg_val) \
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(((reg_val)&GPU_FAULTSTATUS_JASID_MASK) >> GPU_FAULTSTATUS_JASID_SHIFT)
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#define GPU_FAULTSTATUS_JASID_SET(reg_val, value) \
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(((reg_val) & ~GPU_FAULTSTATUS_JASID_MASK) | \
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(((value) << GPU_FAULTSTATUS_JASID_SHIFT) & GPU_FAULTSTATUS_JASID_MASK))
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#define GPU_FAULTSTATUS_SOURCE_ID_SHIFT 16
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#define GPU_FAULTSTATUS_SOURCE_ID_MASK \
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(0xFFFFul << GPU_FAULTSTATUS_SOURCE_ID_SHIFT)
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/* End GPU_FAULTSTATUS register */
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/* GPU_FAULTSTATUS_ACCESS_TYPE values */
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#define GPU_FAULTSTATUS_ACCESS_TYPE_ATOMIC 0x0
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#define GPU_FAULTSTATUS_ACCESS_TYPE_EXECUTE 0x1
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#define GPU_FAULTSTATUS_ACCESS_TYPE_READ 0x2
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#define GPU_FAULTSTATUS_ACCESS_TYPE_WRITE 0x3
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/* End of GPU_FAULTSTATUS_ACCESS_TYPE values */
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/* Implementation-dependent exception codes used to indicate CSG
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* and CS errors that are not specified in the specs.
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*/
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#define GPU_EXCEPTION_TYPE_SW_FAULT_0 ((__u8)0x70)
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#define GPU_EXCEPTION_TYPE_SW_FAULT_1 ((__u8)0x71)
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#define GPU_EXCEPTION_TYPE_SW_FAULT_2 ((__u8)0x72)
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/* GPU_FAULTSTATUS_EXCEPTION_TYPE values */
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#define GPU_FAULTSTATUS_EXCEPTION_TYPE_OK 0x00
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#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_BUS_FAULT 0x80
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#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_SHAREABILITY_FAULT 0x88
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#define GPU_FAULTSTATUS_EXCEPTION_TYPE_SYSTEM_SHAREABILITY_FAULT 0x89
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#define GPU_FAULTSTATUS_EXCEPTION_TYPE_GPU_CACHEABILITY_FAULT 0x8A
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/* End of GPU_FAULTSTATUS_EXCEPTION_TYPE values */
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#define GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT GPU_U(10)
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#define GPU_FAULTSTATUS_ADDRESS_VALID_MASK (GPU_U(0x1) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)
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#define GPU_FAULTSTATUS_ADDRESS_VALID_GET(reg_val) \
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(((reg_val)&GPU_FAULTSTATUS_ADDRESS_VALID_MASK) >> GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT)
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#define GPU_FAULTSTATUS_ADDRESS_VALID_SET(reg_val, value) \
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(((reg_val) & ~GPU_FAULTSTATUS_ADDRESS_VALID_MASK) | \
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(((value) << GPU_FAULTSTATUS_ADDRESS_VALID_SHIFT) & GPU_FAULTSTATUS_ADDRESS_VALID_MASK))
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/* IRQ flags */
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#define GPU_FAULT (1 << 0) /* A GPU Fault has occurred */
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#define GPU_PROTECTED_FAULT (1 << 1) /* A GPU fault has occurred in protected mode */
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#define RESET_COMPLETED (1 << 8) /* Set when a reset has completed. */
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#define POWER_CHANGED_SINGLE (1 << 9) /* Set when a single core has finished powering up or down. */
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#define POWER_CHANGED_ALL (1 << 10) /* Set when all cores have finished powering up or down. */
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#define CLEAN_CACHES_COMPLETED (1 << 17) /* Set when a cache clean operation has completed. */
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#define DOORBELL_MIRROR (1 << 18) /* Mirrors the doorbell interrupt line to the CPU */
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#define MCU_STATUS_GPU_IRQ (1 << 19) /* MCU requires attention */
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/*
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* In Debug build,
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* GPU_IRQ_REG_COMMON | POWER_CHANGED_SINGLE is used to clear and unmask interupts sources of GPU_IRQ
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* by writing it onto GPU_IRQ_CLEAR/MASK registers.
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*
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* In Release build,
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* GPU_IRQ_REG_COMMON is used.
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*
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* Note:
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* CLEAN_CACHES_COMPLETED - Used separately for cache operation.
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* DOORBELL_MIRROR - Do not have it included for GPU_IRQ_REG_COMMON
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* as it can't be cleared by GPU_IRQ_CLEAR, thus interrupt storm might happen
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*/
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#define GPU_IRQ_REG_COMMON (GPU_FAULT | GPU_PROTECTED_FAULT | RESET_COMPLETED \
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| POWER_CHANGED_ALL | MCU_STATUS_GPU_IRQ)
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/* GPU_CONTROL_MCU.GPU_IRQ_RAWSTAT */
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#define PRFCNT_SAMPLE_COMPLETED (1 << 16) /* Set when performance count sample has completed */
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#endif /* _UAPI_KBASE_GPU_REGMAP_CSF_H_ */
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