/*
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* This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
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* DWC Ether MAC version 4.00 has been used for developing this code.
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*
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* This only implements the mac core functions for this chip.
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*
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* Copyright (C) 2015 STMicroelectronics Ltd
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* Author: Alexandre Torgue <alexandre.torgue@st.com>
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*/
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#include <linux/crc32.h>
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#include <linux/slab.h>
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#include <linux/ethtool.h>
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#include <linux/io.h>
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#include <net/dsa.h>
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#include "stmmac.h"
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#include "stmmac_pcs.h"
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#include "dwmac4.h"
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#include "dwmac5.h"
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static void dwmac4_core_init(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_CONFIG);
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int mtu = dev->mtu;
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value |= GMAC_CORE_INIT;
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if (mtu > 1500)
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value |= GMAC_CONFIG_2K;
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if (mtu > 2000)
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value |= GMAC_CONFIG_JE;
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if (hw->ps) {
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value |= GMAC_CONFIG_TE;
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value &= hw->link.speed_mask;
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switch (hw->ps) {
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case SPEED_1000:
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value |= hw->link.speed1000;
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break;
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case SPEED_100:
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value |= hw->link.speed100;
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break;
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case SPEED_10:
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value |= hw->link.speed10;
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break;
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}
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}
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writel(value, ioaddr + GMAC_CONFIG);
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/* Enable GMAC interrupts */
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value = GMAC_INT_DEFAULT_ENABLE;
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if (hw->pcs)
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value |= GMAC_PCS_IRQ_DEFAULT;
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writel(value, ioaddr + GMAC_INT_EN);
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}
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static void dwmac4_rx_queue_enable(struct mac_device_info *hw,
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u8 mode, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_RXQ_CTRL0);
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value &= GMAC_RX_QUEUE_CLEAR(queue);
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if (mode == MTL_QUEUE_AVB)
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value |= GMAC_RX_AV_QUEUE_ENABLE(queue);
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else if (mode == MTL_QUEUE_DCB)
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value |= GMAC_RX_DCB_QUEUE_ENABLE(queue);
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writel(value, ioaddr + GMAC_RXQ_CTRL0);
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}
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static void dwmac4_rx_queue_priority(struct mac_device_info *hw,
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u32 prio, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 base_register;
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u32 value;
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base_register = (queue < 4) ? GMAC_RXQ_CTRL2 : GMAC_RXQ_CTRL3;
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if (queue >= 4)
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queue -= 4;
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value = readl(ioaddr + base_register);
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value &= ~GMAC_RXQCTRL_PSRQX_MASK(queue);
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value |= (prio << GMAC_RXQCTRL_PSRQX_SHIFT(queue)) &
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GMAC_RXQCTRL_PSRQX_MASK(queue);
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writel(value, ioaddr + base_register);
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}
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static void dwmac4_tx_queue_priority(struct mac_device_info *hw,
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u32 prio, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 base_register;
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u32 value;
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base_register = (queue < 4) ? GMAC_TXQ_PRTY_MAP0 : GMAC_TXQ_PRTY_MAP1;
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if (queue >= 4)
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queue -= 4;
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value = readl(ioaddr + base_register);
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value &= ~GMAC_TXQCTRL_PSTQX_MASK(queue);
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value |= (prio << GMAC_TXQCTRL_PSTQX_SHIFT(queue)) &
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GMAC_TXQCTRL_PSTQX_MASK(queue);
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writel(value, ioaddr + base_register);
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}
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static void dwmac4_rx_queue_routing(struct mac_device_info *hw,
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u8 packet, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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static const struct stmmac_rx_routing route_possibilities[] = {
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{ GMAC_RXQCTRL_AVCPQ_MASK, GMAC_RXQCTRL_AVCPQ_SHIFT },
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{ GMAC_RXQCTRL_PTPQ_MASK, GMAC_RXQCTRL_PTPQ_SHIFT },
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{ GMAC_RXQCTRL_DCBCPQ_MASK, GMAC_RXQCTRL_DCBCPQ_SHIFT },
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{ GMAC_RXQCTRL_UPQ_MASK, GMAC_RXQCTRL_UPQ_SHIFT },
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{ GMAC_RXQCTRL_MCBCQ_MASK, GMAC_RXQCTRL_MCBCQ_SHIFT },
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};
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value = readl(ioaddr + GMAC_RXQ_CTRL1);
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/* routing configuration */
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value &= ~route_possibilities[packet - 1].reg_mask;
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value |= (queue << route_possibilities[packet-1].reg_shift) &
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route_possibilities[packet - 1].reg_mask;
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/* some packets require extra ops */
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if (packet == PACKET_AVCPQ) {
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value &= ~GMAC_RXQCTRL_TACPQE;
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value |= 0x1 << GMAC_RXQCTRL_TACPQE_SHIFT;
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} else if (packet == PACKET_MCBCQ) {
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value &= ~GMAC_RXQCTRL_MCBCQEN;
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value |= 0x1 << GMAC_RXQCTRL_MCBCQEN_SHIFT;
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}
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writel(value, ioaddr + GMAC_RXQ_CTRL1);
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}
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static void dwmac4_prog_mtl_rx_algorithms(struct mac_device_info *hw,
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u32 rx_alg)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + MTL_OPERATION_MODE);
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value &= ~MTL_OPERATION_RAA;
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switch (rx_alg) {
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case MTL_RX_ALGORITHM_SP:
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value |= MTL_OPERATION_RAA_SP;
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break;
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case MTL_RX_ALGORITHM_WSP:
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value |= MTL_OPERATION_RAA_WSP;
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break;
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default:
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break;
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}
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writel(value, ioaddr + MTL_OPERATION_MODE);
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}
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static void dwmac4_prog_mtl_tx_algorithms(struct mac_device_info *hw,
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u32 tx_alg)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + MTL_OPERATION_MODE);
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value &= ~MTL_OPERATION_SCHALG_MASK;
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switch (tx_alg) {
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case MTL_TX_ALGORITHM_WRR:
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value |= MTL_OPERATION_SCHALG_WRR;
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break;
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case MTL_TX_ALGORITHM_WFQ:
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value |= MTL_OPERATION_SCHALG_WFQ;
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break;
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case MTL_TX_ALGORITHM_DWRR:
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value |= MTL_OPERATION_SCHALG_DWRR;
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break;
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case MTL_TX_ALGORITHM_SP:
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value |= MTL_OPERATION_SCHALG_SP;
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break;
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default:
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break;
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}
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}
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static void dwmac4_set_mtl_tx_queue_weight(struct mac_device_info *hw,
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u32 weight, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
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value &= ~MTL_TXQ_WEIGHT_ISCQW_MASK;
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value |= weight & MTL_TXQ_WEIGHT_ISCQW_MASK;
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writel(value, ioaddr + MTL_TXQX_WEIGHT_BASE_ADDR(queue));
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}
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static void dwmac4_map_mtl_dma(struct mac_device_info *hw, u32 queue, u32 chan)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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if (queue < 4)
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value = readl(ioaddr + MTL_RXQ_DMA_MAP0);
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else
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value = readl(ioaddr + MTL_RXQ_DMA_MAP1);
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if (queue == 0 || queue == 4) {
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value &= ~MTL_RXQ_DMA_Q04MDMACH_MASK;
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value |= MTL_RXQ_DMA_Q04MDMACH(chan);
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} else {
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value &= ~MTL_RXQ_DMA_QXMDMACH_MASK(queue);
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value |= MTL_RXQ_DMA_QXMDMACH(chan, queue);
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}
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if (queue < 4)
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writel(value, ioaddr + MTL_RXQ_DMA_MAP0);
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else
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writel(value, ioaddr + MTL_RXQ_DMA_MAP1);
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}
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static void dwmac4_config_cbs(struct mac_device_info *hw,
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u32 send_slope, u32 idle_slope,
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u32 high_credit, u32 low_credit, u32 queue)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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pr_debug("Queue %d configured as AVB. Parameters:\n", queue);
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pr_debug("\tsend_slope: 0x%08x\n", send_slope);
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pr_debug("\tidle_slope: 0x%08x\n", idle_slope);
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pr_debug("\thigh_credit: 0x%08x\n", high_credit);
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pr_debug("\tlow_credit: 0x%08x\n", low_credit);
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/* enable AV algorithm */
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value = readl(ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
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value |= MTL_ETS_CTRL_AVALG;
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value |= MTL_ETS_CTRL_CC;
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writel(value, ioaddr + MTL_ETSX_CTRL_BASE_ADDR(queue));
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/* configure send slope */
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value = readl(ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
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value &= ~MTL_SEND_SLP_CRED_SSC_MASK;
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value |= send_slope & MTL_SEND_SLP_CRED_SSC_MASK;
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writel(value, ioaddr + MTL_SEND_SLP_CREDX_BASE_ADDR(queue));
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/* configure idle slope (same register as tx weight) */
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dwmac4_set_mtl_tx_queue_weight(hw, idle_slope, queue);
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/* configure high credit */
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value = readl(ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
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value &= ~MTL_HIGH_CRED_HC_MASK;
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value |= high_credit & MTL_HIGH_CRED_HC_MASK;
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writel(value, ioaddr + MTL_HIGH_CREDX_BASE_ADDR(queue));
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/* configure high credit */
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value = readl(ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
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value &= ~MTL_HIGH_CRED_LC_MASK;
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value |= low_credit & MTL_HIGH_CRED_LC_MASK;
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writel(value, ioaddr + MTL_LOW_CREDX_BASE_ADDR(queue));
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}
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static void dwmac4_dump_regs(struct mac_device_info *hw, u32 *reg_space)
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{
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void __iomem *ioaddr = hw->pcsr;
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int i;
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for (i = 0; i < GMAC_REG_NUM; i++)
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reg_space[i] = readl(ioaddr + i * 4);
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}
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static int dwmac4_rx_ipc_enable(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value = readl(ioaddr + GMAC_CONFIG);
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if (hw->rx_csum)
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value |= GMAC_CONFIG_IPC;
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else
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value &= ~GMAC_CONFIG_IPC;
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writel(value, ioaddr + GMAC_CONFIG);
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value = readl(ioaddr + GMAC_CONFIG);
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return !!(value & GMAC_CONFIG_IPC);
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}
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static void dwmac4_pmt(struct mac_device_info *hw, unsigned long mode)
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{
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void __iomem *ioaddr = hw->pcsr;
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unsigned int pmt = 0;
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u32 config;
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if (mode & WAKE_MAGIC) {
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pr_debug("GMAC: WOL Magic frame\n");
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pmt |= power_down | magic_pkt_en;
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}
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if (mode & WAKE_UCAST) {
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pr_debug("GMAC: WOL on global unicast\n");
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pmt |= power_down | global_unicast | wake_up_frame_en;
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}
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if (pmt) {
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/* The receiver must be enabled for WOL before powering down */
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config = readl(ioaddr + GMAC_CONFIG);
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config |= GMAC_CONFIG_RE;
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writel(config, ioaddr + GMAC_CONFIG);
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}
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writel(pmt, ioaddr + GMAC_PMT);
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}
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static void dwmac4_set_umac_addr(struct mac_device_info *hw,
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unsigned char *addr, unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_dwmac4_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac4_get_umac_addr(struct mac_device_info *hw,
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unsigned char *addr, unsigned int reg_n)
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{
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void __iomem *ioaddr = hw->pcsr;
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stmmac_dwmac4_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
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GMAC_ADDR_LOW(reg_n));
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}
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static void dwmac4_set_eee_mode(struct mac_device_info *hw,
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bool en_tx_lpi_clockgating)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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/* Enable the link status receive on RGMII, SGMII ore SMII
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* receive path and instruct the transmit to enter in LPI
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* state.
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*/
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value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
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value |= GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA;
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if (en_tx_lpi_clockgating)
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value |= GMAC4_LPI_CTRL_STATUS_LPITCSE;
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writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
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}
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static void dwmac4_reset_eee_mode(struct mac_device_info *hw)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
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value &= ~(GMAC4_LPI_CTRL_STATUS_LPIEN | GMAC4_LPI_CTRL_STATUS_LPITXA);
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writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
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}
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static void dwmac4_set_eee_pls(struct mac_device_info *hw, int link)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 value;
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value = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
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if (link)
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value |= GMAC4_LPI_CTRL_STATUS_PLS;
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else
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value &= ~GMAC4_LPI_CTRL_STATUS_PLS;
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writel(value, ioaddr + GMAC4_LPI_CTRL_STATUS);
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}
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static void dwmac4_set_eee_timer(struct mac_device_info *hw, int ls, int tw)
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{
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void __iomem *ioaddr = hw->pcsr;
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int value = ((tw & 0xffff)) | ((ls & 0x3ff) << 16);
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/* Program the timers in the LPI timer control register:
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* LS: minimum time (ms) for which the link
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* status from PHY should be ok before transmitting
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* the LPI pattern.
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* TW: minimum time (us) for which the core waits
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* after it has stopped transmitting the LPI pattern.
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*/
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writel(value, ioaddr + GMAC4_LPI_TIMER_CTRL);
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}
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static void dwmac4_set_filter(struct mac_device_info *hw,
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struct net_device *dev)
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{
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void __iomem *ioaddr = (void __iomem *)dev->base_addr;
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unsigned int value = 0;
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if (dev->flags & IFF_PROMISC) {
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value = GMAC_PACKET_FILTER_PR;
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} else if ((dev->flags & IFF_ALLMULTI) ||
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(netdev_mc_count(dev) > HASH_TABLE_SIZE)) {
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/* Pass all multi */
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value = GMAC_PACKET_FILTER_PM;
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/* Set the 64 bits of the HASH tab. To be updated if taller
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* hash table is used
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*/
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writel(0xffffffff, ioaddr + GMAC_HASH_TAB_0_31);
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writel(0xffffffff, ioaddr + GMAC_HASH_TAB_32_63);
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} else if (!netdev_mc_empty(dev)) {
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u32 mc_filter[2];
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struct netdev_hw_addr *ha;
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/* Hash filter for multicast */
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value = GMAC_PACKET_FILTER_HMC;
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memset(mc_filter, 0, sizeof(mc_filter));
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netdev_for_each_mc_addr(ha, dev) {
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/* The upper 6 bits of the calculated CRC are used to
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* index the content of the Hash Table Reg 0 and 1.
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*/
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int bit_nr =
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(bitrev32(~crc32_le(~0, ha->addr, 6)) >> 26);
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/* The most significant bit determines the register
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* to use while the other 5 bits determines the bit
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* within the selected register
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*/
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mc_filter[bit_nr >> 5] |= (1 << (bit_nr & 0x1F));
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}
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writel(mc_filter[0], ioaddr + GMAC_HASH_TAB_0_31);
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writel(mc_filter[1], ioaddr + GMAC_HASH_TAB_32_63);
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}
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/* Handle multiple unicast addresses */
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if (netdev_uc_count(dev) > hw->unicast_filter_entries) {
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/* Switch to promiscuous mode if more than 128 addrs
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* are required
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*/
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value |= GMAC_PACKET_FILTER_PR;
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} else {
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struct netdev_hw_addr *ha;
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int reg = 1;
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netdev_for_each_uc_addr(ha, dev) {
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dwmac4_set_umac_addr(hw, ha->addr, reg);
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reg++;
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}
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while (reg <= GMAC_MAX_PERFECT_ADDRESSES) {
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writel(0, ioaddr + GMAC_ADDR_HIGH(reg));
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writel(0, ioaddr + GMAC_ADDR_LOW(reg));
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reg++;
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}
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}
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writel(value, ioaddr + GMAC_PACKET_FILTER);
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}
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static void dwmac4_flow_ctrl(struct mac_device_info *hw, unsigned int duplex,
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unsigned int fc, unsigned int pause_time,
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u32 tx_cnt)
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{
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void __iomem *ioaddr = hw->pcsr;
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unsigned int flow = 0;
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u32 queue = 0;
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pr_debug("GMAC Flow-Control:\n");
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if (fc & FLOW_RX) {
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pr_debug("\tReceive Flow-Control ON\n");
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flow |= GMAC_RX_FLOW_CTRL_RFE;
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}
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writel(flow, ioaddr + GMAC_RX_FLOW_CTRL);
|
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if (fc & FLOW_TX) {
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pr_debug("\tTransmit Flow-Control ON\n");
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if (duplex)
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pr_debug("\tduplex mode: PAUSE %d\n", pause_time);
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for (queue = 0; queue < tx_cnt; queue++) {
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flow = GMAC_TX_FLOW_CTRL_TFE;
|
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if (duplex)
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flow |=
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(pause_time << GMAC_TX_FLOW_CTRL_PT_SHIFT);
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writel(flow, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
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}
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} else {
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for (queue = 0; queue < tx_cnt; queue++)
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writel(0, ioaddr + GMAC_QX_TX_FLOW_CTRL(queue));
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}
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}
|
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static void dwmac4_ctrl_ane(void __iomem *ioaddr, bool ane, bool srgmi_ral,
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bool loopback)
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{
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dwmac_ctrl_ane(ioaddr, GMAC_PCS_BASE, ane, srgmi_ral, loopback);
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}
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static void dwmac4_rane(void __iomem *ioaddr, bool restart)
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{
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dwmac_rane(ioaddr, GMAC_PCS_BASE, restart);
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}
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static void dwmac4_get_adv_lp(void __iomem *ioaddr, struct rgmii_adv *adv)
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{
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dwmac_get_adv_lp(ioaddr, GMAC_PCS_BASE, adv);
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}
|
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/* RGMII or SMII interface */
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static void dwmac4_phystatus(void __iomem *ioaddr, struct stmmac_extra_stats *x)
|
{
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u32 status;
|
|
status = readl(ioaddr + GMAC_PHYIF_CONTROL_STATUS);
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x->irq_rgmii_n++;
|
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/* Check the link status */
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if (status & GMAC_PHYIF_CTRLSTATUS_LNKSTS) {
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int speed_value;
|
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x->pcs_link = 1;
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speed_value = ((status & GMAC_PHYIF_CTRLSTATUS_SPEED) >>
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GMAC_PHYIF_CTRLSTATUS_SPEED_SHIFT);
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if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_125)
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x->pcs_speed = SPEED_1000;
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else if (speed_value == GMAC_PHYIF_CTRLSTATUS_SPEED_25)
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x->pcs_speed = SPEED_100;
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else
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x->pcs_speed = SPEED_10;
|
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x->pcs_duplex = (status & GMAC_PHYIF_CTRLSTATUS_LNKMOD_MASK);
|
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pr_info("Link is Up - %d/%s\n", (int)x->pcs_speed,
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x->pcs_duplex ? "Full" : "Half");
|
} else {
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x->pcs_link = 0;
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pr_info("Link is Down\n");
|
}
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}
|
|
static int dwmac4_irq_mtl_status(struct mac_device_info *hw, u32 chan)
|
{
|
void __iomem *ioaddr = hw->pcsr;
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u32 mtl_int_qx_status;
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int ret = 0;
|
|
mtl_int_qx_status = readl(ioaddr + MTL_INT_STATUS);
|
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/* Check MTL Interrupt */
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if (mtl_int_qx_status & MTL_INT_QX(chan)) {
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/* read Queue x Interrupt status */
|
u32 status = readl(ioaddr + MTL_CHAN_INT_CTRL(chan));
|
|
if (status & MTL_RX_OVERFLOW_INT) {
|
/* clear Interrupt */
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writel(status | MTL_RX_OVERFLOW_INT,
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ioaddr + MTL_CHAN_INT_CTRL(chan));
|
ret = CORE_IRQ_MTL_RX_OVERFLOW;
|
}
|
}
|
|
return ret;
|
}
|
|
static int dwmac4_irq_status(struct mac_device_info *hw,
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struct stmmac_extra_stats *x)
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{
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void __iomem *ioaddr = hw->pcsr;
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u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
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u32 intr_enable = readl(ioaddr + GMAC_INT_EN);
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int ret = 0;
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/* Discard disabled bits */
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intr_status &= intr_enable;
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/* Not used events (e.g. MMC interrupts) are not handled. */
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if ((intr_status & mmc_tx_irq))
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x->mmc_tx_irq_n++;
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if (unlikely(intr_status & mmc_rx_irq))
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x->mmc_rx_irq_n++;
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if (unlikely(intr_status & mmc_rx_csum_offload_irq))
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x->mmc_rx_csum_offload_irq_n++;
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/* Clear the PMT bits 5 and 6 by reading the PMT status reg */
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if (unlikely(intr_status & pmt_irq)) {
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readl(ioaddr + GMAC_PMT);
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x->irq_receive_pmt_irq_n++;
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}
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/* MAC tx/rx EEE LPI entry/exit interrupts */
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if (intr_status & lpi_irq) {
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/* Clear LPI interrupt by reading MAC_LPI_Control_Status */
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u32 status = readl(ioaddr + GMAC4_LPI_CTRL_STATUS);
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if (status & GMAC4_LPI_CTRL_STATUS_TLPIEN) {
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ret |= CORE_IRQ_TX_PATH_IN_LPI_MODE;
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x->irq_tx_path_in_lpi_mode_n++;
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}
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if (status & GMAC4_LPI_CTRL_STATUS_TLPIEX) {
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ret |= CORE_IRQ_TX_PATH_EXIT_LPI_MODE;
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x->irq_tx_path_exit_lpi_mode_n++;
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}
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if (status & GMAC4_LPI_CTRL_STATUS_RLPIEN)
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x->irq_rx_path_in_lpi_mode_n++;
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if (status & GMAC4_LPI_CTRL_STATUS_RLPIEX)
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x->irq_rx_path_exit_lpi_mode_n++;
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}
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dwmac_pcs_isr(ioaddr, GMAC_PCS_BASE, intr_status, x);
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if (intr_status & PCS_RGSMIIIS_IRQ)
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dwmac4_phystatus(ioaddr, x);
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return ret;
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}
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static void dwmac4_debug(void __iomem *ioaddr, struct stmmac_extra_stats *x,
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u32 rx_queues, u32 tx_queues)
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{
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u32 value;
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u32 queue;
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for (queue = 0; queue < tx_queues; queue++) {
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value = readl(ioaddr + MTL_CHAN_TX_DEBUG(queue));
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if (value & MTL_DEBUG_TXSTSFSTS)
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x->mtl_tx_status_fifo_full++;
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if (value & MTL_DEBUG_TXFSTS)
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x->mtl_tx_fifo_not_empty++;
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if (value & MTL_DEBUG_TWCSTS)
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x->mmtl_fifo_ctrl++;
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if (value & MTL_DEBUG_TRCSTS_MASK) {
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u32 trcsts = (value & MTL_DEBUG_TRCSTS_MASK)
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>> MTL_DEBUG_TRCSTS_SHIFT;
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if (trcsts == MTL_DEBUG_TRCSTS_WRITE)
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x->mtl_tx_fifo_read_ctrl_write++;
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else if (trcsts == MTL_DEBUG_TRCSTS_TXW)
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x->mtl_tx_fifo_read_ctrl_wait++;
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else if (trcsts == MTL_DEBUG_TRCSTS_READ)
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x->mtl_tx_fifo_read_ctrl_read++;
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else
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x->mtl_tx_fifo_read_ctrl_idle++;
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}
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if (value & MTL_DEBUG_TXPAUSED)
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x->mac_tx_in_pause++;
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}
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for (queue = 0; queue < rx_queues; queue++) {
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value = readl(ioaddr + MTL_CHAN_RX_DEBUG(queue));
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if (value & MTL_DEBUG_RXFSTS_MASK) {
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u32 rxfsts = (value & MTL_DEBUG_RXFSTS_MASK)
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>> MTL_DEBUG_RRCSTS_SHIFT;
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if (rxfsts == MTL_DEBUG_RXFSTS_FULL)
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x->mtl_rx_fifo_fill_level_full++;
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else if (rxfsts == MTL_DEBUG_RXFSTS_AT)
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x->mtl_rx_fifo_fill_above_thresh++;
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else if (rxfsts == MTL_DEBUG_RXFSTS_BT)
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x->mtl_rx_fifo_fill_below_thresh++;
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else
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x->mtl_rx_fifo_fill_level_empty++;
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}
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if (value & MTL_DEBUG_RRCSTS_MASK) {
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u32 rrcsts = (value & MTL_DEBUG_RRCSTS_MASK) >>
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MTL_DEBUG_RRCSTS_SHIFT;
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if (rrcsts == MTL_DEBUG_RRCSTS_FLUSH)
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x->mtl_rx_fifo_read_ctrl_flush++;
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else if (rrcsts == MTL_DEBUG_RRCSTS_RSTAT)
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x->mtl_rx_fifo_read_ctrl_read_data++;
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else if (rrcsts == MTL_DEBUG_RRCSTS_RDATA)
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x->mtl_rx_fifo_read_ctrl_status++;
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else
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x->mtl_rx_fifo_read_ctrl_idle++;
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}
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if (value & MTL_DEBUG_RWCSTS)
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x->mtl_rx_fifo_ctrl_active++;
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}
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/* GMAC debug */
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value = readl(ioaddr + GMAC_DEBUG);
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if (value & GMAC_DEBUG_TFCSTS_MASK) {
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u32 tfcsts = (value & GMAC_DEBUG_TFCSTS_MASK)
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>> GMAC_DEBUG_TFCSTS_SHIFT;
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if (tfcsts == GMAC_DEBUG_TFCSTS_XFER)
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x->mac_tx_frame_ctrl_xfer++;
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else if (tfcsts == GMAC_DEBUG_TFCSTS_GEN_PAUSE)
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x->mac_tx_frame_ctrl_pause++;
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else if (tfcsts == GMAC_DEBUG_TFCSTS_WAIT)
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x->mac_tx_frame_ctrl_wait++;
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else
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x->mac_tx_frame_ctrl_idle++;
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}
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if (value & GMAC_DEBUG_TPESTS)
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x->mac_gmii_tx_proto_engine++;
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if (value & GMAC_DEBUG_RFCFCSTS_MASK)
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x->mac_rx_frame_ctrl_fifo = (value & GMAC_DEBUG_RFCFCSTS_MASK)
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>> GMAC_DEBUG_RFCFCSTS_SHIFT;
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if (value & GMAC_DEBUG_RPESTS)
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x->mac_gmii_rx_proto_engine++;
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}
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const struct stmmac_ops dwmac4_ops = {
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.core_init = dwmac4_core_init,
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.set_mac = stmmac_set_mac,
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.rx_ipc = dwmac4_rx_ipc_enable,
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.rx_queue_enable = dwmac4_rx_queue_enable,
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.rx_queue_prio = dwmac4_rx_queue_priority,
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.tx_queue_prio = dwmac4_tx_queue_priority,
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.rx_queue_routing = dwmac4_rx_queue_routing,
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.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
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.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
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.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
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.map_mtl_to_dma = dwmac4_map_mtl_dma,
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.config_cbs = dwmac4_config_cbs,
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.dump_regs = dwmac4_dump_regs,
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.host_irq_status = dwmac4_irq_status,
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.host_mtl_irq_status = dwmac4_irq_mtl_status,
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.flow_ctrl = dwmac4_flow_ctrl,
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.pmt = dwmac4_pmt,
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.set_umac_addr = dwmac4_set_umac_addr,
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.get_umac_addr = dwmac4_get_umac_addr,
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.set_eee_mode = dwmac4_set_eee_mode,
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.reset_eee_mode = dwmac4_reset_eee_mode,
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.set_eee_timer = dwmac4_set_eee_timer,
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.set_eee_pls = dwmac4_set_eee_pls,
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.pcs_ctrl_ane = dwmac4_ctrl_ane,
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.pcs_rane = dwmac4_rane,
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.pcs_get_adv_lp = dwmac4_get_adv_lp,
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.debug = dwmac4_debug,
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.set_filter = dwmac4_set_filter,
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};
|
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const struct stmmac_ops dwmac410_ops = {
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.core_init = dwmac4_core_init,
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.set_mac = stmmac_dwmac4_set_mac,
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.rx_ipc = dwmac4_rx_ipc_enable,
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.rx_queue_enable = dwmac4_rx_queue_enable,
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.rx_queue_prio = dwmac4_rx_queue_priority,
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.tx_queue_prio = dwmac4_tx_queue_priority,
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.rx_queue_routing = dwmac4_rx_queue_routing,
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.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
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.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
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.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
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.map_mtl_to_dma = dwmac4_map_mtl_dma,
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.config_cbs = dwmac4_config_cbs,
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.dump_regs = dwmac4_dump_regs,
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.host_irq_status = dwmac4_irq_status,
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.host_mtl_irq_status = dwmac4_irq_mtl_status,
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.flow_ctrl = dwmac4_flow_ctrl,
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.pmt = dwmac4_pmt,
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.set_umac_addr = dwmac4_set_umac_addr,
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.get_umac_addr = dwmac4_get_umac_addr,
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.set_eee_mode = dwmac4_set_eee_mode,
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.reset_eee_mode = dwmac4_reset_eee_mode,
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.set_eee_timer = dwmac4_set_eee_timer,
|
.set_eee_pls = dwmac4_set_eee_pls,
|
.pcs_ctrl_ane = dwmac4_ctrl_ane,
|
.pcs_rane = dwmac4_rane,
|
.pcs_get_adv_lp = dwmac4_get_adv_lp,
|
.debug = dwmac4_debug,
|
.set_filter = dwmac4_set_filter,
|
};
|
|
const struct stmmac_ops dwmac510_ops = {
|
.core_init = dwmac4_core_init,
|
.set_mac = stmmac_dwmac4_set_mac,
|
.rx_ipc = dwmac4_rx_ipc_enable,
|
.rx_queue_enable = dwmac4_rx_queue_enable,
|
.rx_queue_prio = dwmac4_rx_queue_priority,
|
.tx_queue_prio = dwmac4_tx_queue_priority,
|
.rx_queue_routing = dwmac4_rx_queue_routing,
|
.prog_mtl_rx_algorithms = dwmac4_prog_mtl_rx_algorithms,
|
.prog_mtl_tx_algorithms = dwmac4_prog_mtl_tx_algorithms,
|
.set_mtl_tx_queue_weight = dwmac4_set_mtl_tx_queue_weight,
|
.map_mtl_to_dma = dwmac4_map_mtl_dma,
|
.config_cbs = dwmac4_config_cbs,
|
.dump_regs = dwmac4_dump_regs,
|
.host_irq_status = dwmac4_irq_status,
|
.host_mtl_irq_status = dwmac4_irq_mtl_status,
|
.flow_ctrl = dwmac4_flow_ctrl,
|
.pmt = dwmac4_pmt,
|
.set_umac_addr = dwmac4_set_umac_addr,
|
.get_umac_addr = dwmac4_get_umac_addr,
|
.set_eee_mode = dwmac4_set_eee_mode,
|
.reset_eee_mode = dwmac4_reset_eee_mode,
|
.set_eee_timer = dwmac4_set_eee_timer,
|
.set_eee_pls = dwmac4_set_eee_pls,
|
.pcs_ctrl_ane = dwmac4_ctrl_ane,
|
.pcs_rane = dwmac4_rane,
|
.pcs_get_adv_lp = dwmac4_get_adv_lp,
|
.debug = dwmac4_debug,
|
.set_filter = dwmac4_set_filter,
|
.safety_feat_config = dwmac5_safety_feat_config,
|
.safety_feat_irq_status = dwmac5_safety_feat_irq_status,
|
.safety_feat_dump = dwmac5_safety_feat_dump,
|
.rxp_config = dwmac5_rxp_config,
|
.flex_pps_config = dwmac5_flex_pps_config,
|
};
|
|
int dwmac4_setup(struct stmmac_priv *priv)
|
{
|
struct mac_device_info *mac = priv->hw;
|
|
dev_info(priv->device, "\tDWMAC4/5\n");
|
|
priv->dev->priv_flags |= IFF_UNICAST_FLT;
|
mac->pcsr = priv->ioaddr;
|
mac->multicast_filter_bins = priv->plat->multicast_filter_bins;
|
mac->unicast_filter_entries = priv->plat->unicast_filter_entries;
|
mac->mcast_bits_log2 = 0;
|
|
if (mac->multicast_filter_bins)
|
mac->mcast_bits_log2 = ilog2(mac->multicast_filter_bins);
|
|
mac->link.duplex = GMAC_CONFIG_DM;
|
mac->link.speed10 = GMAC_CONFIG_PS;
|
mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
|
mac->link.speed1000 = 0;
|
mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
|
mac->mii.addr = GMAC_MDIO_ADDR;
|
mac->mii.data = GMAC_MDIO_DATA;
|
mac->mii.addr_shift = 21;
|
mac->mii.addr_mask = GENMASK(25, 21);
|
mac->mii.reg_shift = 16;
|
mac->mii.reg_mask = GENMASK(20, 16);
|
mac->mii.clk_csr_shift = 8;
|
mac->mii.clk_csr_mask = GENMASK(11, 8);
|
|
return 0;
|
}
|
