From 48ddf4fb999931942c359350fb31cd557514e1c6 Mon Sep 17 00:00:00 2001
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From: Chenxi Mao <maochenxi@eswin.com>
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Date: Mon, 20 Apr 2020 15:27:22 +0800
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Subject: [PATCH 1/1] adb: Support riscv64
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---
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include/cutils/atomic-inline.h | 2 +
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include/cutils/atomic-riscv64.h | 156 ++++++++++++++++++++++++++++++++
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2 files changed, 158 insertions(+)
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create mode 100644 include/cutils/atomic-riscv64.h
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diff --git a/include/cutils/atomic-inline.h b/include/cutils/atomic-inline.h
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index a31e913579..b5dc38209c 100644
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--- a/include/cutils/atomic-inline.h
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+++ b/include/cutils/atomic-inline.h
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@@ -55,6 +55,8 @@ extern "C" {
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#include <cutils/atomic-mips64.h>
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#elif defined(__mips__)
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#include <cutils/atomic-mips.h>
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+#elif defined(__riscv) && __riscv_xlen == 64
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+#include <cutils/atomic-riscv64.h>
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#else
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#error atomic operations are unsupported
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#endif
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diff --git a/include/cutils/atomic-riscv64.h b/include/cutils/atomic-riscv64.h
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new file mode 100644
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index 0000000000..2664db5a86
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--- /dev/null
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+++ b/include/cutils/atomic-riscv64.h
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@@ -0,0 +1,156 @@
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+/*
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+ * Copyright (C) 2014 The Android Open Source Project
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+ * All rights reserved.
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+ *
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+ * Redistribution and use in source and binary forms, with or without
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+ * modification, are permitted provided that the following conditions
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+ * are met:
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+ * * Redistributions of source code must retain the above copyright
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+ * notice, this list of conditions and the following disclaimer.
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+ * * Redistributions in binary form must reproduce the above copyright
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+ * notice, this list of conditions and the following disclaimer in
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+ * the documentation and/or other materials provided with the
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+ * distribution.
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+ *
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+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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+ * SUCH DAMAGE.
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+ */
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+
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+#ifndef ANDROID_CUTILS_ATOMIC_RISCV64_H
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+#define ANDROID_CUTILS_ATOMIC_RISCV64_H
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+
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+#include <stdint.h>
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+
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+#ifndef ANDROID_ATOMIC_INLINE
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+#define ANDROID_ATOMIC_INLINE inline __attribute__((always_inline))
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+#endif
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+
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+/*
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+ TODOAArch64: Revisit the below functions and check for potential
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+ optimizations using assembly code or otherwise.
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+*/
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+
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+extern ANDROID_ATOMIC_INLINE
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+void android_compiler_barrier(void)
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+{
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+ __asm__ __volatile__ ("" : : : "memory");
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+void android_memory_barrier(void)
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+{
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+ __asm__ __volatile__ ("fence rw,rw" : : : "memory");
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int32_t android_atomic_acquire_load(volatile const int32_t *ptr)
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+{
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+ int32_t value = *ptr;
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+ android_memory_barrier();
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+ return value;
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int32_t android_atomic_release_load(volatile const int32_t *ptr)
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+{
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+ android_memory_barrier();
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+ return *ptr;
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+void android_atomic_acquire_store(int32_t value, volatile int32_t *ptr)
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+{
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+ *ptr = value;
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+ android_memory_barrier();
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+void android_atomic_release_store(int32_t value, volatile int32_t *ptr)
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+{
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+ android_memory_barrier();
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+ *ptr = value;
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int android_atomic_cas(int32_t old_value, int32_t new_value,
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+ volatile int32_t *ptr)
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+{
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+ return __sync_val_compare_and_swap(ptr, old_value, new_value) != old_value;
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int android_atomic_acquire_cas(int32_t old_value, int32_t new_value,
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+ volatile int32_t *ptr)
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+{
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+ int status = android_atomic_cas(old_value, new_value, ptr);
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+ android_memory_barrier();
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+ return status;
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int android_atomic_release_cas(int32_t old_value, int32_t new_value,
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+ volatile int32_t *ptr)
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+{
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+ android_memory_barrier();
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+ return android_atomic_cas(old_value, new_value, ptr);
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int32_t android_atomic_add(int32_t increment, volatile int32_t *ptr)
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+{
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+ int32_t prev, status;
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+ android_memory_barrier();
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+ do {
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+ prev = *ptr;
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+ status = android_atomic_cas(prev, prev + increment, ptr);
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+ } while (__builtin_expect(status != 0, 0));
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+ return prev;
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int32_t android_atomic_inc(volatile int32_t *addr)
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+{
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+ return android_atomic_add(1, addr);
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int32_t android_atomic_dec(volatile int32_t *addr)
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+{
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+ return android_atomic_add(-1, addr);
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int32_t android_atomic_and(int32_t value, volatile int32_t *ptr)
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+{
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+ int32_t prev, status;
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+ android_memory_barrier();
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+ do {
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+ prev = *ptr;
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+ status = android_atomic_cas(prev, prev & value, ptr);
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+ } while (__builtin_expect(status != 0, 0));
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+ return prev;
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+}
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+
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+extern ANDROID_ATOMIC_INLINE
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+int32_t android_atomic_or(int32_t value, volatile int32_t *ptr)
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+{
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+ int32_t prev, status;
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+ android_memory_barrier();
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+ do {
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+ prev = *ptr;
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+ status = android_atomic_cas(prev, prev | value, ptr);
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+ } while (__builtin_expect(status != 0, 0));
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+ return prev;
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+}
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+
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+#endif /* ANDROID_CUTILS_ATOMIC_RISCV_H */
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--
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2.17.1
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