From b0a64ddebb517a1678c44d9baf24d8bbe39d02cd Mon Sep 17 00:00:00 2001
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From: Khem Raj <raj.khem@gmail.com>
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Date: Tue, 29 Jan 2019 13:15:07 -0800
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Subject: [PATCH] asm: Delete .func/.endfunc directives
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These are useful only with stabs debug format, which is not used on
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linux systems, gas ignores them silently, but clang assembler does not
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and rightly so.
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Signed-off-by: Khem Raj <raj.khem@gmail.com>
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---
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aarch64-asm.S | 14 +-------------
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arm-neon.S | 24 ------------------------
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mips-32.S | 5 ++---
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x86-sse2.S | 21 ++++++++++-----------
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4 files changed, 13 insertions(+), 51 deletions(-)
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diff --git a/aarch64-asm.S b/aarch64-asm.S
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index 842b9e2..165c8ac 100644
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--- a/aarch64-asm.S
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+++ b/aarch64-asm.S
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@@ -31,8 +31,7 @@
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.macro asm_function function_name
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.global \function_name
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- .type \function_name,%function
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-.func \function_name
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+ .type \function_name,%function
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\function_name:
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DST .req x0
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SRC .req x1
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@@ -54,7 +53,6 @@ asm_function aligned_block_copy_ldpstp_x_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_copy_ldpstp_q_aarch64
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0:
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@@ -67,7 +65,6 @@ asm_function aligned_block_copy_ldpstp_q_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_copy_ldpstp_q_pf32_l2strm_aarch64
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0:
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@@ -82,7 +79,6 @@ asm_function aligned_block_copy_ldpstp_q_pf32_l2strm_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_copy_ldpstp_q_pf64_l2strm_aarch64
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0:
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@@ -96,7 +92,6 @@ asm_function aligned_block_copy_ldpstp_q_pf64_l2strm_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_copy_ldpstp_q_pf32_l1keep_aarch64
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0:
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@@ -111,7 +106,6 @@ asm_function aligned_block_copy_ldpstp_q_pf32_l1keep_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_copy_ldpstp_q_pf64_l1keep_aarch64
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0:
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@@ -125,7 +119,6 @@ asm_function aligned_block_copy_ldpstp_q_pf64_l1keep_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_fill_stp_x_aarch64
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0:
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@@ -137,7 +130,6 @@ asm_function aligned_block_fill_stp_x_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_fill_stp_q_aarch64
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0:
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@@ -147,7 +139,6 @@ asm_function aligned_block_fill_stp_q_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_fill_stnp_x_aarch64
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0:
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@@ -159,7 +150,6 @@ asm_function aligned_block_fill_stnp_x_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_fill_stnp_q_aarch64
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0:
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@@ -169,7 +159,6 @@ asm_function aligned_block_fill_stnp_q_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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asm_function aligned_block_copy_ld1st1_aarch64
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0:
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@@ -180,6 +169,5 @@ asm_function aligned_block_copy_ld1st1_aarch64
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subs SIZE, SIZE, #64
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bgt 0b
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ret
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-.endfunc
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#endif
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diff --git a/arm-neon.S b/arm-neon.S
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index 4db78ce..9631d82 100644
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--- a/arm-neon.S
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+++ b/arm-neon.S
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@@ -32,7 +32,6 @@
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.macro asm_function function_name
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.global \function_name
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-.func \function_name
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\function_name:
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DST .req r0
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SRC .req r1
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@@ -66,7 +65,6 @@ asm_function aligned_block_read_neon
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vpadd.u32 d31, d31, d31
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vmov.u32 r0, d31[0]
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bx lr
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-.endfunc
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/* Actually this calculates a sum of 32-bit values */
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asm_function aligned_block_read_pf32_neon
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@@ -97,7 +95,6 @@ asm_function aligned_block_read_pf32_neon
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vpadd.u32 d31, d31, d31
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vmov.u32 r0, d31[0]
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bx lr
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-.endfunc
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/* Actually this calculates a sum of 32-bit values */
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asm_function aligned_block_read_pf64_neon
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@@ -127,7 +124,6 @@ asm_function aligned_block_read_pf64_neon
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vpadd.u32 d31, d31, d31
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vmov.u32 r0, d31[0]
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bx lr
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-.endfunc
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/* Actually this calculates a sum of 32-bit values */
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asm_function aligned_block_read2_neon
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@@ -156,7 +152,6 @@ asm_function aligned_block_read2_neon
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vpadd.u32 d31, d31, d31
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vmov.u32 r0, d31[0]
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bx lr
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-.endfunc
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/* Actually this calculates a sum of 32-bit values */
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asm_function aligned_block_read2_pf32_neon
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@@ -187,7 +182,6 @@ asm_function aligned_block_read2_pf32_neon
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vpadd.u32 d31, d31, d31
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vmov.u32 r0, d31[0]
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bx lr
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-.endfunc
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/* Actually this calculates a sum of 32-bit values */
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asm_function aligned_block_read2_pf64_neon
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@@ -217,7 +211,6 @@ asm_function aligned_block_read2_pf64_neon
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vpadd.u32 d31, d31, d31
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vmov.u32 r0, d31[0]
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bx lr
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-.endfunc
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asm_function aligned_block_copy_neon
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0:
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@@ -226,7 +219,6 @@ asm_function aligned_block_copy_neon
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subs SIZE, SIZE, #32
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bgt 0b
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bx lr
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-.endfunc
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asm_function aligned_block_copy_unrolled_neon
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vpush {d8-d15}
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@@ -244,7 +236,6 @@ asm_function aligned_block_copy_unrolled_neon
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bgt 0b
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vpop {d8-d15}
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bx lr
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-.endfunc
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asm_function aligned_block_copy_pf32_neon
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0:
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@@ -254,7 +245,6 @@ asm_function aligned_block_copy_pf32_neon
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subs SIZE, SIZE, #32
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bgt 0b
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bx lr
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-.endfunc
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asm_function aligned_block_copy_unrolled_pf32_neon
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vpush {d8-d15}
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@@ -280,7 +270,6 @@ asm_function aligned_block_copy_unrolled_pf32_neon
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bgt 0b
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vpop {d8-d15}
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bx lr
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-.endfunc
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asm_function aligned_block_copy_pf64_neon
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0:
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@@ -292,7 +281,6 @@ asm_function aligned_block_copy_pf64_neon
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subs SIZE, SIZE, #64
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bgt 0b
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bx lr
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-.endfunc
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asm_function aligned_block_copy_unrolled_pf64_neon
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vpush {d8-d15}
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@@ -314,7 +302,6 @@ asm_function aligned_block_copy_unrolled_pf64_neon
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bgt 0b
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vpop {d8-d15}
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bx lr
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-.endfunc
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asm_function aligned_block_copy_backwards_neon
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add SRC, SRC, SIZE
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@@ -328,7 +315,6 @@ asm_function aligned_block_copy_backwards_neon
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subs SIZE, SIZE, #32
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bgt 0b
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bx lr
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-.endfunc
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asm_function aligned_block_copy_backwards_pf32_neon
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add SRC, SRC, SIZE
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@@ -343,7 +329,6 @@ asm_function aligned_block_copy_backwards_pf32_neon
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subs SIZE, SIZE, #32
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bgt 0b
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bx lr
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-.endfunc
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asm_function aligned_block_copy_backwards_pf64_neon
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add SRC, SRC, SIZE
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@@ -360,7 +345,6 @@ asm_function aligned_block_copy_backwards_pf64_neon
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subs SIZE, SIZE, #64
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bgt 0b
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bx lr
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-.endfunc
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asm_function aligned_block_fill_neon
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vld1.8 {d0, d1, d2, d3}, [SRC]!
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@@ -370,7 +354,6 @@ asm_function aligned_block_fill_neon
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subs SIZE, SIZE, #64
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bgt 0b
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bx lr
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-.endfunc
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asm_function aligned_block_fill_backwards_neon
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add SRC, SRC, SIZE
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@@ -383,7 +366,6 @@ asm_function aligned_block_fill_backwards_neon
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subs SIZE, SIZE, #32
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bgt 0b
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bx lr
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-.endfunc
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/* some code for older ARM processors */
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@@ -398,7 +380,6 @@ asm_function aligned_block_fill_stm4_armv4
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subs SIZE, SIZE, #64
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bgt 0b
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pop {r4-r12, pc}
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-.endfunc
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asm_function aligned_block_fill_stm8_armv4
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push {r4-r12, lr}
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@@ -409,7 +390,6 @@ asm_function aligned_block_fill_stm8_armv4
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subs SIZE, SIZE, #64
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bgt 0b
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pop {r4-r12, pc}
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-.endfunc
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asm_function aligned_block_fill_strd_armv5te
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push {r4-r12, lr}
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@@ -426,7 +406,6 @@ asm_function aligned_block_fill_strd_armv5te
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subs SIZE, SIZE, #64
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bgt 0b
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pop {r4-r12, pc}
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-.endfunc
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asm_function aligned_block_copy_incr_armv5te
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push {r4-r12, lr}
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@@ -442,7 +421,6 @@ asm_function aligned_block_copy_incr_armv5te
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stmia DST!, {r8-r11}
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bgt 0b
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pop {r4-r12, pc}
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-.endfunc
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asm_function aligned_block_copy_wrap_armv5te
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push {r4-r12, lr}
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@@ -458,7 +436,6 @@ asm_function aligned_block_copy_wrap_armv5te
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stmia DST!, {r8-r11}
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bgt 0b
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pop {r4-r12, pc}
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-.endfunc
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asm_function aligned_block_copy_vfp
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push {r4-r12, lr}
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@@ -470,6 +447,5 @@ asm_function aligned_block_copy_vfp
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bgt 0b
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vpop {d8-d15}
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pop {r4-r12, pc}
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-.endfunc
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#endif
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diff --git a/mips-32.S b/mips-32.S
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index 17b2b7f..4f7ddae 100644
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--- a/mips-32.S
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+++ b/mips-32.S
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@@ -32,7 +32,6 @@
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.macro asm_function function_name
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.global \function_name
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.type \function_name, @function
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- .func \function_name
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\function_name:
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.endm
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@@ -93,7 +92,7 @@ asm_function aligned_block_fill_pf32_mips32
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2:
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jr $ra
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nop
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-.endfunc
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+
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/*
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* void aligned_block_copy_pf32_mips32(int64_t *dst, int64_t *src, int size)
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@@ -178,6 +177,6 @@ asm_function aligned_block_copy_pf32_mips32
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lw $s7, 28($sp)
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jr $ra
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addi $sp, $sp, 32
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-.endfunc
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+
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#endif
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diff --git a/x86-sse2.S b/x86-sse2.S
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index d8840e4..409031b 100644
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--- a/x86-sse2.S
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+++ b/x86-sse2.S
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@@ -30,7 +30,6 @@
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.macro asm_function_helper function_name
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.global \function_name
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-.func \function_name
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\function_name:
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#ifdef __amd64__
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#ifdef _WIN64
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@@ -90,7 +89,7 @@ asm_function aligned_block_copy_movsb
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pop3 edi esi ecx
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#endif
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ret
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-.endfunc
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+
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asm_function aligned_block_copy_movsd
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0:
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@@ -110,7 +109,7 @@ asm_function aligned_block_copy_movsd
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pop3 edi esi ecx
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#endif
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ret
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-.endfunc
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+
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asm_function aligned_block_copy_sse2
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0:
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@@ -127,7 +126,7 @@ asm_function aligned_block_copy_sse2
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sub SIZE, 64
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jg 0b
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ret
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-.endfunc
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+
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asm_function aligned_block_copy_nt_sse2
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0:
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@@ -144,7 +143,7 @@ asm_function aligned_block_copy_nt_sse2
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sub SIZE, 64
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jg 0b
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ret
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-.endfunc
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+
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asm_function aligned_block_copy_pf32_sse2
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0:
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@@ -163,7 +162,7 @@ asm_function aligned_block_copy_pf32_sse2
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sub SIZE, 64
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jg 0b
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ret
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-.endfunc
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+
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asm_function aligned_block_copy_nt_pf32_sse2
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0:
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@@ -182,7 +181,7 @@ asm_function aligned_block_copy_nt_pf32_sse2
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sub SIZE, 64
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jg 0b
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ret
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-.endfunc
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+
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asm_function aligned_block_copy_pf64_sse2
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0:
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@@ -200,7 +199,7 @@ asm_function aligned_block_copy_pf64_sse2
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sub SIZE, 64
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jg 0b
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ret
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-.endfunc
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+
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asm_function aligned_block_copy_nt_pf64_sse2
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0:
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@@ -218,7 +217,7 @@ asm_function aligned_block_copy_nt_pf64_sse2
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sub SIZE, 64
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jg 0b
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ret
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-.endfunc
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+
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asm_function aligned_block_fill_sse2
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movdqa xmm0, [SRC + 0]
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@@ -231,7 +230,7 @@ asm_function aligned_block_fill_sse2
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sub SIZE, 64
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jg 0b
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ret
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-.endfunc
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+
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asm_function aligned_block_fill_nt_sse2
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movdqa xmm0, [SRC + 0]
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@@ -244,7 +243,7 @@ asm_function aligned_block_fill_nt_sse2
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sub SIZE, 64
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jg 0b
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ret
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-.endfunc
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+
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/*****************************************************************************/
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