/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <phy.h>
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#include <fm_eth.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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static u32 port_to_devdisr[] = {
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[FM1_DTSEC1] = MPC85xx_DEVDISR_TSEC1,
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[FM1_DTSEC2] = MPC85xx_DEVDISR_TSEC2,
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};
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static int is_device_disabled(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 devdisr = in_be32(&gur->devdisr);
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return port_to_devdisr[port] & devdisr;
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}
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void fman_disable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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/* don't allow disabling of DTSEC1 as its needed for MDIO */
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if (port == FM1_DTSEC1)
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return;
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setbits_be32(&gur->devdisr, port_to_devdisr[port]);
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}
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void fman_enable_port(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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clrbits_be32(&gur->devdisr, port_to_devdisr[port]);
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}
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phy_interface_t fman_port_enet_if(enum fm_port port)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 pordevsr = in_be32(&gur->pordevsr);
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if (is_device_disabled(port))
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return PHY_INTERFACE_MODE_NONE;
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/* DTSEC1 can be SGMII, RGMII or RMII */
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if (port == FM1_DTSEC1) {
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if (is_serdes_configured(SGMII_FM1_DTSEC1))
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return PHY_INTERFACE_MODE_SGMII;
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if (pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS) {
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if (pordevsr & MPC85xx_PORDEVSR_TSEC1_PRTC)
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return PHY_INTERFACE_MODE_RGMII;
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else
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return PHY_INTERFACE_MODE_RMII;
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}
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}
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/* DTSEC2 only supports SGMII or RGMII */
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if (port == FM1_DTSEC2) {
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if (is_serdes_configured(SGMII_FM1_DTSEC2))
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return PHY_INTERFACE_MODE_SGMII;
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if (pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS)
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return PHY_INTERFACE_MODE_RGMII;
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}
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return PHY_INTERFACE_MODE_NONE;
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}
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