/*
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* Copyright (c) 2017 Yifeng Zhao <yifeng.zhao@rock-chips.com>
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* Copyright (c) 2017 Paweł Jarosz <paweljarosz3691@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <inttypes.h>
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#include <nand.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/nand.h>
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#include <linux/mtd/partitions.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_ROCKCHIP_RK3568
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#define NANDC_V9_BOOTROM_ECC 16
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#else
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#define NANDC_V9_BOOTROM_ECC 70
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#endif
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#define NANDC_V9_NUM_BANKS 4
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#define NANDC_V9_DEF_TIMEOUT 20000
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#define NANDC_V9_READ 0
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#define NANDC_V9_WRITE 1
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#define NANDC_REG_V9_FMCTL 0x00
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#define NANDC_REG_V9_FMWAIT 0x04
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#define NANDC_REG_V9_FLCTL 0x10
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#define NANDC_REG_V9_BCHCTL 0x20
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#define NANDC_REG_V9_DMA_CFG 0x30
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#define NANDC_REG_V9_DMA_BUF0 0x34
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#define NANDC_REG_V9_DMA_BUF1 0x38
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#define NANDC_REG_V9_DMA_ST 0x40
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#define NANDC_REG_V9_VER 0x80
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#define NANDC_REG_V9_INTEN 0x120
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#define NANDC_REG_V9_INTCLR 0x124
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#define NANDC_REG_V9_INTST 0x128
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#define NANDC_REG_V9_BCHST 0x150
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#define NANDC_REG_V9_SPARE0 0x200
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#define NANDC_REG_V9_SPARE1 0x204
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#define NANDC_REG_V9_RANDMZ 0x208
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#define NANDC_REG_V9_BANK0 0x800
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#define NANDC_REG_V9_SRAM0 0x1000
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#define NANDC_REG_V9_SRAM_SIZE 0x400
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#define NANDC_REG_V9_DATA 0x00
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#define NANDC_REG_V9_ADDR 0x04
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#define NANDC_REG_V9_CMD 0x08
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/* FMCTL */
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#define NANDC_V9_FM_WP BIT(8)
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#define NANDC_V9_FM_CE_SEL_M 0xFF
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#define NANDC_V9_FM_CE_SEL(x) (1 << (x))
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#define NANDC_V9_FM_FREADY BIT(9)
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/* FLCTL */
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#define NANDC_V9_FL_RST BIT(0)
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#define NANDC_V9_FL_DIR_S 0x1
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#define NANDC_V9_FL_XFER_START BIT(2)
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#define NANDC_V9_FL_XFER_EN BIT(3)
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#define NANDC_V9_FL_ST_BUF_S 0x4
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#define NANDC_V9_FL_XFER_COUNT BIT(5)
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#define NANDC_V9_FL_ACORRECT BIT(10)
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#define NANDC_V9_FL_XFER_READY BIT(20)
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#define NANDC_V9_FL_ASYNC_TOG_MIX BIT(29)
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/* BCHCTL */
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#define NAND_V9_BCH_MODE_S 25
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#define NAND_V9_BCH_MODE_M 0x7
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/* BCHST */
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#define NANDC_V9_BCH0_ST_ERR BIT(2)
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#define NANDC_V9_BCH1_ST_ERR BIT(18)
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#define NANDC_V9_ECC_ERR_CNT0(x) (((x) & (0x7F << 3)) >> 3)
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#define NANDC_V9_ECC_ERR_CNT1(x) (((x) & (0x7F << 19)) >> 19)
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struct rk_nand {
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uint32_t banks[NANDC_V9_NUM_BANKS];
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struct nand_hw_control controller;
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uint32_t ecc_strength;
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struct mtd_info mtd;
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bool bootromblocks;
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void __iomem *regs;
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int selected_bank;
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struct udevice *dev;
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};
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static struct nand_ecclayout nand_oob_fix = {
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.eccbytes = 24,
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.eccpos = {
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4, 5, 6, 7, 8, 9, 10
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},
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.oobfree = {
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{
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.offset = 0,
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.length = 4
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}
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}
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};
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static inline struct rk_nand *to_rknand(struct nand_hw_control *ctrl)
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{
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return container_of(ctrl, struct rk_nand, controller);
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}
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static void rockchip_nand_init(struct rk_nand *rknand)
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{
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writel(0, rknand->regs + NANDC_REG_V9_RANDMZ);
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writel(0, rknand->regs + NANDC_REG_V9_DMA_CFG);
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writel(0, rknand->regs + NANDC_REG_V9_BCHCTL);
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writel(NANDC_V9_FM_WP, rknand->regs + NANDC_REG_V9_FMCTL);
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writel(0x1081, rknand->regs + NANDC_REG_V9_FMWAIT);
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}
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static void rockchip_nand_select_chip(struct mtd_info *mtd, int chipnr)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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void __iomem *bank_base;
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uint32_t reg;
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int banknr;
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reg = readl(rknand->regs + NANDC_REG_V9_FMCTL);
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reg &= ~NANDC_V9_FM_CE_SEL_M;
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if (chipnr == -1) {
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banknr = -1;
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} else {
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banknr = rknand->banks[chipnr];
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bank_base = rknand->regs + NANDC_REG_V9_BANK0 + banknr * 0x100;
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chip->IO_ADDR_R = bank_base;
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chip->IO_ADDR_W = bank_base;
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reg |= 1 << banknr;
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}
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writel(reg, rknand->regs + NANDC_REG_V9_FMCTL);
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rknand->selected_bank = banknr;
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}
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static void rockchip_nand_cmd_ctrl(struct mtd_info *mtd,
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int dat,
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unsigned int ctrl)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0
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+ rknand->selected_bank * 0x100;
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if (ctrl & NAND_CTRL_CHANGE) {
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if (ctrl & NAND_ALE)
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bank_base += NANDC_REG_V9_ADDR;
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else if (ctrl & NAND_CLE)
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bank_base += NANDC_REG_V9_CMD;
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chip->IO_ADDR_W = bank_base;
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}
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if (dat != NAND_CMD_NONE)
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writeb(dat & 0xFF, chip->IO_ADDR_W);
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}
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static void rockchip_nand_read_buf(struct mtd_info *mtd,
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uint8_t *buf,
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int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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int offs = 0;
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void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0
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+ rknand->selected_bank * 0x100;
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for (offs = 0; offs < len; offs++)
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buf[offs] = readb(bank_base);
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}
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static void rockchip_nand_write_buf(struct mtd_info *mtd,
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const uint8_t *buf,
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int len)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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int offs = 0;
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void __iomem *bank_base = rknand->regs + NANDC_REG_V9_BANK0
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+ rknand->selected_bank * 0x100;
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for (offs = 0; offs < len; offs++)
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writeb(buf[offs], bank_base);
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}
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static uint8_t rockchip_nand_read_byte(struct mtd_info *mtd)
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{
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uint8_t ret;
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rockchip_nand_read_buf(mtd, &ret, 1);
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return ret;
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}
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static int rockchip_nand_dev_ready(struct mtd_info *mtd)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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if (readl(rknand->regs + NANDC_REG_V9_FMCTL) & NANDC_V9_FM_FREADY)
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return 1;
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return 0;
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}
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static int rockchip_nand_hw_ecc_setup(struct mtd_info *mtd,
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struct nand_ecc_ctrl *ecc,
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uint32_t strength)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct rk_nand *rknand = to_rknand(chip->controller);
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u32 reg;
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ecc->strength = strength;
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ecc->bytes = DIV_ROUND_UP(ecc->strength * 14, 8);
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ecc->bytes = ALIGN(ecc->bytes, 2);
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switch (ecc->strength) {
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case 70:
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reg = 0x00000001;
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break;
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case 60:
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reg = 0x06000001;
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break;
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case 40:
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reg = 0x04000001;
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break;
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case 16:
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reg = 0x02000001;
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break;
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default:
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return -EINVAL;
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}
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writel(reg, rknand->regs + NANDC_REG_V9_BCHCTL);
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return 0;
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}
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static void rockchip_nand_pio_xfer_start(struct rk_nand *rknand,
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u8 dir,
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u8 st_buf)
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{
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u32 reg;
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reg = (dir << NANDC_V9_FL_DIR_S) | (st_buf << NANDC_V9_FL_ST_BUF_S) |
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NANDC_V9_FL_XFER_EN | NANDC_V9_FL_XFER_COUNT |
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NANDC_V9_FL_ACORRECT | NANDC_V9_FL_ASYNC_TOG_MIX;
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writel(reg, rknand->regs + NANDC_REG_V9_FLCTL);
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reg |= NANDC_V9_FL_XFER_START;
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writel(reg, rknand->regs + NANDC_REG_V9_FLCTL);
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}
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static int rockchip_nand_wait_pio_xfer_done(struct rk_nand *rknand)
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{
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int timeout = NANDC_V9_DEF_TIMEOUT;
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int reg;
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while (timeout--) {
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reg = readl(rknand->regs + NANDC_REG_V9_FLCTL);
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if ((reg & NANDC_V9_FL_XFER_READY) != 0)
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break;
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udelay(1);
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}
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if (timeout == 0)
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return -1;
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return 0;
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}
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static void rockchip_nand_read_extra_oob(struct mtd_info *mtd, u8 *oob)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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int offset = ((ecc->bytes + ecc->prepad) * ecc->steps);
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int len = mtd->oobsize - offset;
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if (len <= 0)
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return;
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chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset + mtd->writesize, -1);
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rockchip_nand_read_buf(mtd, oob + offset, len);
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}
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static void rockchip_nand_write_extra_oob(struct mtd_info *mtd, u8 *oob)
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{
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struct nand_chip *chip = mtd_to_nand(mtd);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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int offset = ((ecc->bytes + ecc->prepad) * ecc->steps);
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int len = mtd->oobsize - offset;
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if (len <= 0)
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return;
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chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset + mtd->writesize, -1);
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rockchip_nand_write_buf(mtd, oob + offset, len);
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}
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static int rockchip_nand_hw_syndrome_pio_read_page(struct mtd_info *mtd,
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struct nand_chip *chip,
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uint8_t *buf,
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int oob_required,
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int page)
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{
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struct rk_nand *rknand = to_rknand(chip->controller);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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void __iomem *sram_base = rknand->regs + NANDC_REG_V9_SRAM0;
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unsigned int max_bitflips = 0;
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int ret, step, bch_st;
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int offset = page * mtd->writesize;
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if (rknand->bootromblocks && (offset < (4 * mtd->erasesize)))
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rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V9_BOOTROM_ECC);
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rockchip_nand_pio_xfer_start(rknand, NANDC_V9_READ, 0);
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for (step = 0; step < ecc->steps; step++) {
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int data_off = step * ecc->size;
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int oob_off = step * (ecc->bytes + ecc->prepad);
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u8 *data = buf + data_off;
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u8 *oob = chip->oob_poi + oob_off;
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ret = rockchip_nand_wait_pio_xfer_done(rknand);
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if (ret)
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return ret;
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bch_st = readl(rknand->regs + NANDC_REG_V9_BCHST);
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if (bch_st & NANDC_V9_BCH0_ST_ERR) {
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mtd->ecc_stats.failed++;
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max_bitflips = -1;
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} else {
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ret = NANDC_V9_ECC_ERR_CNT0(bch_st);
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mtd->ecc_stats.corrected += ret;
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max_bitflips = max_t(unsigned int, max_bitflips, ret);
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}
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if ((step + 1) < ecc->steps)
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rockchip_nand_pio_xfer_start(rknand, NANDC_V9_READ,
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(step + 1) & 0x1);
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memcpy_fromio(data, sram_base + NANDC_REG_V9_SRAM_SIZE *
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(step & 1), ecc->size);
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if (step & 1)
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memcpy_fromio(oob, rknand->regs + NANDC_REG_V9_SPARE1, 4);
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else
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memcpy_fromio(oob, rknand->regs + NANDC_REG_V9_SPARE0, 4);
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}
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rockchip_nand_read_extra_oob(mtd, chip->oob_poi);
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if (rknand->bootromblocks)
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rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength);
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return max_bitflips;
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}
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static uint32_t rockchip_nand_make_bootrom_compat(struct mtd_info *mtd,
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int page,
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const u8 *oob,
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bool bootromblocks)
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{
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int pages_per_block = mtd->erasesize / mtd->writesize;
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int offset = page * mtd->writesize;
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if ((offset < (2 * mtd->erasesize)) || !(page % 2) ||
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(offset >= (7 * mtd->erasesize)) || !bootromblocks)
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return oob[3] | (oob[2] << 8) | (oob[1] << 16) | (oob[0] << 24);
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return (page % pages_per_block + 1) * 4;
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}
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static int rockchip_nand_hw_syndrome_pio_write_page(struct mtd_info *mtd,
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struct nand_chip *chip,
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const uint8_t *buf,
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int oob_required,
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int page)
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{
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struct rk_nand *rknand = to_rknand(chip->controller);
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struct nand_ecc_ctrl *ecc = &chip->ecc;
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void __iomem *sram_base = rknand->regs + NANDC_REG_V9_SRAM0;
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int ret, index, step = 0;
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int offset = page * mtd->writesize;
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int data_off = step * ecc->size;
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int oob_off = step * (ecc->bytes + ecc->prepad);
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const u8 *data = buf + data_off;
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const u8 *oob = chip->oob_poi + oob_off;
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if (rknand->bootromblocks && (offset < (7 * mtd->erasesize)))
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rockchip_nand_hw_ecc_setup(mtd, ecc, NANDC_V9_BOOTROM_ECC);
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index = rockchip_nand_make_bootrom_compat(mtd, page, oob,
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rknand->bootromblocks);
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memcpy_toio(sram_base, data, ecc->size);
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memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE0, &index, ecc->prepad);
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for (step = 1; step <= ecc->steps; step++) {
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rockchip_nand_pio_xfer_start(rknand, NANDC_V9_WRITE,
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(step - 1) & 0x1);
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data_off = step * ecc->size;
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oob_off = step * (ecc->bytes + ecc->prepad);
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data = buf + data_off;
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oob = chip->oob_poi + oob_off;
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if (step < ecc->steps) {
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memcpy_toio(sram_base + NANDC_REG_V9_SRAM_SIZE *
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(step & 1), data, ecc->size);
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if (step & 1)
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memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE1,
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oob, ecc->prepad);
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else
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memcpy_toio(rknand->regs + NANDC_REG_V9_SPARE0,
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oob, ecc->prepad);
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}
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ret = rockchip_nand_wait_pio_xfer_done(rknand);
|
if (ret)
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return ret;
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}
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rockchip_nand_write_extra_oob(mtd, chip->oob_poi);
|
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if (rknand->bootromblocks)
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rockchip_nand_hw_ecc_setup(mtd, ecc, rknand->ecc_strength);
|
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return 0;
|
}
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static const u8 strengths[] = {70, 60, 40, 16};
|
|
static int rockchip_nand_ecc_max_strength(struct mtd_info *mtd,
|
struct nand_ecc_ctrl *ecc)
|
{
|
uint32_t max_strength, index;
|
|
max_strength = ((mtd->oobsize / ecc->steps) - ecc->prepad) * 8 / 14;
|
|
for (index = 0; index < ARRAY_SIZE(strengths); index++)
|
if (max_strength >= strengths[index])
|
break;
|
|
if (index >= ARRAY_SIZE(strengths))
|
return -ENOTSUPP;
|
|
return strengths[index];
|
}
|
|
static bool rockchip_nand_strength_is_valid(int strength)
|
{
|
uint32_t index;
|
|
for (index = 0; index < ARRAY_SIZE(strengths); index++)
|
if (strength == strengths[index])
|
break;
|
|
if (index == ARRAY_SIZE(strengths))
|
return false;
|
|
return true;
|
}
|
|
static int rockchip_nand_hw_ecc_ctrl_init(struct mtd_info *mtd,
|
struct nand_ecc_ctrl *ecc)
|
{
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
struct rk_nand *rknand = to_rknand(chip->controller);
|
uint32_t strength;
|
int index;
|
|
ecc->prepad = 4;
|
ecc->steps = mtd->writesize / ecc->size;
|
|
if (fdtdec_get_bool(gd->fdt_blob, chip->flash_node,
|
"rockchip,protect-bootrom-blocks"))
|
rknand->bootromblocks = true;
|
else
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rknand->bootromblocks = false;
|
|
if (rockchip_nand_strength_is_valid(ecc->strength))
|
strength = ecc->strength;
|
else
|
strength = rockchip_nand_ecc_max_strength(mtd, ecc);
|
|
rockchip_nand_hw_ecc_setup(mtd, ecc, strength);
|
|
rknand->ecc_strength = ecc->strength;
|
|
nand_oob_fix.eccbytes = ecc->bytes * ecc->steps;
|
for (index = 0; index < ecc->bytes; index++)
|
nand_oob_fix.eccpos[index] = index + ecc->prepad;
|
ecc->layout = &nand_oob_fix;
|
|
if (mtd->oobsize < ((ecc->bytes + ecc->prepad) * ecc->steps)) {
|
return -EINVAL;
|
}
|
|
return 0;
|
}
|
|
static int rockchip_nand_ecc_init(struct mtd_info *mtd,
|
struct nand_ecc_ctrl *ecc)
|
{
|
int ret;
|
|
switch (ecc->mode) {
|
case NAND_ECC_HW:
|
case NAND_ECC_HW_SYNDROME:
|
ret = rockchip_nand_hw_ecc_ctrl_init(mtd, ecc);
|
if (ret)
|
return ret;
|
ecc->read_page = rockchip_nand_hw_syndrome_pio_read_page;
|
ecc->write_page = rockchip_nand_hw_syndrome_pio_write_page;
|
break;
|
case NAND_ECC_SOFT_BCH:
|
case NAND_ECC_NONE:
|
case NAND_ECC_SOFT:
|
break;
|
default:
|
return -EINVAL;
|
}
|
|
return 0;
|
}
|
|
static int rockchip_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
|
{
|
int page, res = 0;
|
struct nand_chip *chip = mtd_to_nand(mtd);
|
u16 bad = 0xff;
|
int chipnr = (int)(ofs >> chip->chip_shift);
|
|
page = (int)(ofs >> chip->page_shift) & chip->pagemask;
|
chip->select_chip(mtd, chipnr);
|
chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
|
if(rockchip_nand_hw_syndrome_pio_read_page(mtd,
|
chip, chip->buffers->databuf, 0, page) == -1) {
|
/* first page of the block*/
|
chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
|
bad = chip->read_byte(mtd);
|
if (bad != 0xFF)
|
res = 1;
|
/* second page of the block*/
|
chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
|
page + 1);
|
bad = chip->read_byte(mtd);
|
if (bad != 0xFF)
|
res = 1;
|
/* last page of the block */
|
page += ((mtd->erasesize - mtd->writesize) >> chip->chip_shift);
|
page--;
|
chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos, page);
|
bad = chip->read_byte(mtd);
|
if (bad != 0xFF)
|
res = 1;
|
}
|
chip->select_chip(mtd, -1);
|
if (res)
|
printf("%s 0x%x %x %x\n", __func__, page, res, bad);
|
return res;
|
}
|
|
static int rockchip_nand_chip_init(int node, struct rk_nand *rknand, int devnum)
|
{
|
const void *blob = gd->fdt_blob;
|
struct nand_chip *chip;
|
struct mtd_info *mtd;
|
int ret;
|
|
chip = kzalloc(sizeof(*chip), GFP_KERNEL);
|
|
chip->chip_delay = 50;
|
chip->flash_node = node;
|
chip->select_chip = rockchip_nand_select_chip;
|
chip->cmd_ctrl = rockchip_nand_cmd_ctrl;
|
chip->read_buf = rockchip_nand_read_buf;
|
chip->write_buf = rockchip_nand_write_buf;
|
chip->read_byte = rockchip_nand_read_byte;
|
chip->dev_ready = rockchip_nand_dev_ready;
|
chip->controller = &rknand->controller;
|
chip->block_bad = rockchip_nand_block_bad;
|
chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
|
chip->options = NAND_NO_SUBPAGE_WRITE;
|
|
rknand->banks[devnum] = fdtdec_get_int(blob, node, "reg", -1);
|
|
if (rknand->banks[devnum] < 0)
|
return -EINVAL;
|
|
mtd = nand_to_mtd(chip);
|
mtd->dev = rknand->dev;
|
if (rknand->dev)
|
rknand->dev->priv = mtd;
|
|
ret = nand_scan_ident(mtd, 1, NULL);
|
if (ret)
|
return ret;
|
|
ret = rockchip_nand_ecc_init(mtd, &chip->ecc);
|
if (ret) {
|
debug("rockchip_nand_ecc_init failed: %d\n", ret);
|
return ret;
|
}
|
|
ret = nand_scan_tail(mtd);
|
if (ret) {
|
debug("nand_scan_tail failed: %d\n", ret);
|
return ret;
|
}
|
|
ret = nand_register(devnum, mtd);
|
if (ret) {
|
debug("Failed to register mtd device: %d\n", ret);
|
return ret;
|
}
|
memcpy(&rknand->mtd, mtd, sizeof(struct mtd_info));
|
|
return 0;
|
}
|
|
static int rockchip_nand_chips_init(int node, struct rk_nand *rknand)
|
{
|
const void *blob = gd->fdt_blob;
|
int nand_node;
|
int ret, i = 0;
|
|
for (nand_node = fdt_first_subnode(blob, node); nand_node >= 0;
|
nand_node = fdt_next_subnode(blob, nand_node)) {
|
ret = rockchip_nand_chip_init(nand_node, rknand, i++);
|
if (ret)
|
return ret;
|
}
|
|
return 0;
|
}
|
|
#ifdef CONFIG_NAND_ROCKCHIP_DT
|
static const struct udevice_id rockchip_nandc_ids[] = {
|
{ .compatible = "rockchip,rk-nandc" },
|
{ }
|
};
|
|
static int rockchip_nandc_probe(struct udevice *dev)
|
{
|
const void *blob = gd->fdt_blob;
|
struct rk_nand *rknand = dev_get_priv(dev);
|
struct mtd_info *mtd = dev_get_uclass_priv(dev);
|
fdt_addr_t regs;
|
int ret = 0, node;
|
|
node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
|
|
rknand->dev = dev;
|
|
regs = dev_read_addr(dev);
|
if (regs == FDT_ADDR_T_NONE) {
|
debug("Nand address not found\n");
|
return ret;
|
}
|
|
rknand->regs = (void *)regs;
|
|
spin_lock_init(&rknand->controller.lock);
|
init_waitqueue_head(&rknand->controller.wq);
|
|
rockchip_nand_init(rknand);
|
|
ret = rockchip_nand_chips_init(node, rknand);
|
if (ret)
|
debug("Failed to init nand chips\n");
|
|
memcpy(mtd, &rknand->mtd, sizeof(struct mtd_info));
|
|
return ret;
|
}
|
|
static int rockchip_nandc_bind(struct udevice *udev)
|
{
|
int ret = 0;
|
|
#ifdef CONFIG_MTD_BLK
|
struct udevice *bdev;
|
|
ret = blk_create_devicef(udev, "mtd_blk", "blk", IF_TYPE_MTD,
|
BLK_MTD_NAND, 512, 0, &bdev);
|
if (ret)
|
printf("Cannot create block device\n");
|
#endif
|
return ret;
|
}
|
|
U_BOOT_DRIVER(rk_nandc_v9) = {
|
.name = "rk_nandc_v9",
|
.id = UCLASS_MTD,
|
.of_match = rockchip_nandc_ids,
|
.bind = rockchip_nandc_bind,
|
.probe = rockchip_nandc_probe,
|
.priv_auto_alloc_size = sizeof(struct rk_nand),
|
};
|
|
void board_nand_init(void)
|
{
|
struct udevice *dev;
|
int ret;
|
|
ret = uclass_get_device_by_driver(UCLASS_MTD,
|
DM_GET_DRIVER(rk_nandc_v9),
|
&dev);
|
if (ret && ret != -ENODEV)
|
pr_err("Failed to initialize NAND controller. (error %d)\n",
|
ret);
|
}
|
#else
|
|
void board_nand_init(void)
|
{
|
const void *blob = gd->fdt_blob;
|
struct rk_nand *rknand;
|
fdt_addr_t regs;
|
int node;
|
int ret;
|
|
rknand = kzalloc(sizeof(*rknand), GFP_KERNEL);
|
|
node = fdtdec_next_compatible(blob, 0, COMPAT_ROCKCHIP_NANDC);
|
|
if (node < 0) {
|
debug("Nand node not found\n");
|
goto err;
|
}
|
|
if (!fdtdec_get_is_enabled(blob, node)) {
|
debug("Nand disabled in device tree\n");
|
goto err;
|
}
|
|
regs = fdt_get_base_address(blob, node);
|
if (regs == FDT_ADDR_T_NONE) {
|
debug("Nand address not found\n");
|
goto err;
|
}
|
|
rknand->regs = (void *)regs;
|
|
spin_lock_init(&rknand->controller.lock);
|
init_waitqueue_head(&rknand->controller.wq);
|
|
rockchip_nand_init(rknand);
|
|
ret = rockchip_nand_chips_init(node, rknand);
|
if (ret) {
|
debug("Failed to init nand chips\n");
|
goto err;
|
}
|
|
return;
|
err:
|
kfree(rknand);
|
}
|
|
#endif
|
|
int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
|
{
|
struct mtd_info *mtd;
|
size_t length = size;
|
|
mtd = get_nand_dev_by_index(0);
|
return nand_read_skip_bad(mtd, offs, &length, NULL, size, (u_char *)dst);
|
}
|
|
void nand_deselect(void) {}
|
