/*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2016 Bin Meng <bmeng.cn@gmail.com>
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*
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* Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _BAYTRAIL_IRQ_H_
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#define _BAYTRAIL_IRQ_H_
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#define PIRQA_APIC_IRQ 16
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#define PIRQB_APIC_IRQ 17
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#define PIRQC_APIC_IRQ 18
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#define PIRQD_APIC_IRQ 19
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#define PIRQE_APIC_IRQ 20
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#define PIRQF_APIC_IRQ 21
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#define PIRQG_APIC_IRQ 22
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#define PIRQH_APIC_IRQ 23
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/* The below IRQs are for when devices are in ACPI mode */
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#define LPE_DMA0_IRQ 24
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#define LPE_DMA1_IRQ 25
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#define LPE_SSP0_IRQ 26
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#define LPE_SSP1_IRQ 27
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#define LPE_SSP2_IRQ 28
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#define LPE_IPC2HOST_IRQ 29
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#define LPSS_I2C1_IRQ 32
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#define LPSS_I2C2_IRQ 33
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#define LPSS_I2C3_IRQ 34
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#define LPSS_I2C4_IRQ 35
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#define LPSS_I2C5_IRQ 36
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#define LPSS_I2C6_IRQ 37
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#define LPSS_I2C7_IRQ 38
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#define LPSS_HSUART1_IRQ 39
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#define LPSS_HSUART2_IRQ 40
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#define LPSS_SPI_IRQ 41
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#define LPSS_DMA1_IRQ 42
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#define LPSS_DMA2_IRQ 43
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#define SCC_EMMC_IRQ 44
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#define SCC_SDIO_IRQ 46
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#define SCC_SD_IRQ 47
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#define GPIO_NC_IRQ 48
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#define GPIO_SC_IRQ 49
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#define GPIO_SUS_IRQ 50
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/* GPIO direct / dedicated IRQs */
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#define GPIO_S0_DED_IRQ_0 51
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#define GPIO_S0_DED_IRQ_1 52
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#define GPIO_S0_DED_IRQ_2 53
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#define GPIO_S0_DED_IRQ_3 54
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#define GPIO_S0_DED_IRQ_4 55
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#define GPIO_S0_DED_IRQ_5 56
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#define GPIO_S0_DED_IRQ_6 57
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#define GPIO_S0_DED_IRQ_7 58
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#define GPIO_S0_DED_IRQ_8 59
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#define GPIO_S0_DED_IRQ_9 60
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#define GPIO_S0_DED_IRQ_10 61
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#define GPIO_S0_DED_IRQ_11 62
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#define GPIO_S0_DED_IRQ_12 63
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#define GPIO_S0_DED_IRQ_13 64
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#define GPIO_S0_DED_IRQ_14 65
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#define GPIO_S0_DED_IRQ_15 66
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#define GPIO_S5_DED_IRQ_0 67
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#define GPIO_S5_DED_IRQ_1 68
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#define GPIO_S5_DED_IRQ_2 69
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#define GPIO_S5_DED_IRQ_3 70
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#define GPIO_S5_DED_IRQ_4 71
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#define GPIO_S5_DED_IRQ_5 72
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#define GPIO_S5_DED_IRQ_6 73
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#define GPIO_S5_DED_IRQ_7 74
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#define GPIO_S5_DED_IRQ_8 75
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#define GPIO_S5_DED_IRQ_9 76
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#define GPIO_S5_DED_IRQ_10 77
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#define GPIO_S5_DED_IRQ_11 78
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#define GPIO_S5_DED_IRQ_12 79
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#define GPIO_S5_DED_IRQ_13 80
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#define GPIO_S5_DED_IRQ_14 81
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#define GPIO_S5_DED_IRQ_15 82
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/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */
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#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot
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#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot
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#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot)
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#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot)
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#endif /* _BAYTRAIL_IRQ_H_ */
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