#ifndef _ASM_CPU_SH7785_H_
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#define _ASM_CPU_SH7785_H_
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/*
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* Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
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* Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
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* Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define CACHE_OC_NUM_WAYS 1
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#define CCR_CACHE_INIT 0x0000090b
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/* Exceptions */
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#define TRA 0xFF000020
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#define EXPEVT 0xFF000024
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#define INTEVT 0xFF000028
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/* Cache Controller */
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#define CCR 0xFF00001C
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#define QACR0 0xFF000038
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#define QACR1 0xFF00003C
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#define RAMCR 0xFF000074
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/* Watchdog Timer and Reset */
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#define WTCNT WDTCNT
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#define WDTST 0xFFCC0000
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#define WDTCSR 0xFFCC0004
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#define WDTBST 0xFFCC0008
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#define WDTCNT 0xFFCC0010
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#define WDTBCNT 0xFFCC0018
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/* Timer Unit */
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#define TMU_BASE 0xFFD80000
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/* Serial Communication Interface with FIFO */
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#define SCIF1_BASE 0xffeb0000
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/* LBSC */
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#define MMSELR 0xfc400020
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#define LBSC_BASE 0xff800000
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#define BCR (LBSC_BASE + 0x1000)
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#define CS0BCR (LBSC_BASE + 0x2000)
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#define CS1BCR (LBSC_BASE + 0x2010)
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#define CS2BCR (LBSC_BASE + 0x2020)
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#define CS3BCR (LBSC_BASE + 0x2030)
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#define CS4BCR (LBSC_BASE + 0x2040)
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#define CS5BCR (LBSC_BASE + 0x2050)
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#define CS6BCR (LBSC_BASE + 0x2060)
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#define CS0WCR (LBSC_BASE + 0x2008)
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#define CS1WCR (LBSC_BASE + 0x2018)
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#define CS2WCR (LBSC_BASE + 0x2028)
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#define CS3WCR (LBSC_BASE + 0x2038)
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#define CS4WCR (LBSC_BASE + 0x2048)
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#define CS5WCR (LBSC_BASE + 0x2058)
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#define CS6WCR (LBSC_BASE + 0x2068)
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#define CS5PCR (LBSC_BASE + 0x2070)
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#define CS6PCR (LBSC_BASE + 0x2080)
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/* PCI Controller */
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#define SH7780_PCIECR 0xFE000008
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#define SH7780_PCIVID 0xFE040000
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#define SH7780_PCIDID 0xFE040002
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#define SH7780_PCICMD 0xFE040004
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#define SH7780_PCISTATUS 0xFE040006
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#define SH7780_PCIRID 0xFE040008
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#define SH7780_PCIPIF 0xFE040009
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#define SH7780_PCISUB 0xFE04000A
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#define SH7780_PCIBCC 0xFE04000B
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#define SH7780_PCICLS 0xFE04000C
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#define SH7780_PCILTM 0xFE04000D
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#define SH7780_PCIHDR 0xFE04000E
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#define SH7780_PCIBIST 0xFE04000F
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#define SH7780_PCIIBAR 0xFE040010
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#define SH7780_PCIMBAR0 0xFE040014
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#define SH7780_PCIMBAR1 0xFE040018
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#define SH7780_PCISVID 0xFE04002C
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#define SH7780_PCISID 0xFE04002E
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#define SH7780_PCICP 0xFE040034
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#define SH7780_PCIINTLINE 0xFE04003C
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#define SH7780_PCIINTPIN 0xFE04003D
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#define SH7780_PCIMINGNT 0xFE04003E
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#define SH7780_PCIMAXLAT 0xFE04003F
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#define SH7780_PCICID 0xFE040040
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#define SH7780_PCINIP 0xFE040041
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#define SH7780_PCIPMC 0xFE040042
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#define SH7780_PCIPMCSR 0xFE040044
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#define SH7780_PCIPMCSRBSE 0xFE040046
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#define SH7780_PCI_CDD 0xFE040047
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#define SH7780_PCICR 0xFE040100
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#define SH7780_PCILSR0 0xFE040104
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#define SH7780_PCILSR1 0xFE040108
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#define SH7780_PCILAR0 0xFE04010C
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#define SH7780_PCILAR1 0xFE040110
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#define SH7780_PCIIR 0xFE040114
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#define SH7780_PCIIMR 0xFE040118
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#define SH7780_PCIAIR 0xFE04011C
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#define SH7780_PCICIR 0xFE040120
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#define SH7780_PCIAINT 0xFE040130
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#define SH7780_PCIAINTM 0xFE040134
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#define SH7780_PCIBMIR 0xFE040138
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#define SH7780_PCIPAR 0xFE0401C0
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#define SH7780_PCIPINT 0xFE0401CC
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#define SH7780_PCIPINTM 0xFE0401D0
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#define SH7780_PCIMBR0 0xFE0401E0
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#define SH7780_PCIMBMR0 0xFE0401E4
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#define SH7780_PCIMBR1 0xFE0401E8
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#define SH7780_PCIMBMR1 0xFE0401EC
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#define SH7780_PCIMBR2 0xFE0401F0
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#define SH7780_PCIMBMR2 0xFE0401F4
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#define SH7780_PCIIOBR 0xFE0401F8
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#define SH7780_PCIIOBMR 0xFE0401FC
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#define SH7780_PCICSCR0 0xFE040210
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#define SH7780_PCICSCR1 0xFE040214
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#define SH7780_PCICSAR0 0xFE040218
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#define SH7780_PCICSAR1 0xFE04021C
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#define SH7780_PCIPDR 0xFE040220
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#endif /* _ASM_CPU_SH7780_H_ */
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