/*
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* Startup Code for MIPS32 CPU-core
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*
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* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/mipsregs.h>
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#ifndef CONFIG_SYS_INIT_SP_ADDR
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
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CONFIG_SYS_INIT_SP_OFFSET)
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#endif
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#ifdef CONFIG_32BIT
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# define MIPS_RELOC 3
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# define STATUS_SET 0
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#endif
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#ifdef CONFIG_64BIT
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# ifdef CONFIG_SYS_LITTLE_ENDIAN
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# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
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(((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
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# else
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# define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
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((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
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# endif
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# define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
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# define STATUS_SET ST0_KX
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#endif
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.set noreorder
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.macro init_wr sel
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MTC0 zero, CP0_WATCHLO,\sel
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mtc0 t1, CP0_WATCHHI,\sel
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mfc0 t0, CP0_WATCHHI,\sel
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bgez t0, wr_done
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nop
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.endm
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.macro uhi_mips_exception
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move k0, t9 # preserve t9 in k0
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move k1, a0 # preserve a0 in k1
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li t9, 15 # UHI exception operation
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li a0, 0 # Use hard register context
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sdbbp 1 # Invoke UHI operation
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.endm
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.macro setup_stack_gd
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li t0, -16
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PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
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and sp, t1, t0 # force 16 byte alignment
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PTR_SUBU \
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sp, sp, GD_SIZE # reserve space for gd
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and sp, sp, t0 # force 16 byte alignment
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move k0, sp # save gd pointer
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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li t2, CONFIG_VAL(SYS_MALLOC_F_LEN)
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PTR_SUBU \
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sp, sp, t2 # reserve space for early malloc
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and sp, sp, t0 # force 16 byte alignment
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#endif
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move fp, sp
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/* Clear gd */
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move t0, k0
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1:
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PTR_S zero, 0(t0)
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blt t0, t1, 1b
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PTR_ADDIU t0, PTRSIZE
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#if CONFIG_VAL(SYS_MALLOC_F_LEN)
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PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
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#endif
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.endm
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ENTRY(_start)
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/* U-Boot entry point */
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b reset
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mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing
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#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
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/*
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* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
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* access external NOR flashes. If the board boots from NOR flash the
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* internal BootROM does a blind read at address 0xB0000010 to read the
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* initial configuration for that EBU in order to access the flash
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* device with correct parameters. This config option is board-specific.
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*/
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.org 0x10
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.word CONFIG_SYS_XWAY_EBU_BOOTCFG
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.word 0x0
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#endif
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#if defined(CONFIG_MALTA)
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/*
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* Linux expects the Board ID here.
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*/
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.org 0x10
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.word 0x00000420 # 0x420 (Malta Board with CoreLV)
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.word 0x00000000
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#endif
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#if defined(CONFIG_ROM_EXCEPTION_VECTORS)
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/*
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* Exception vector entry points. When running from ROM, an exception
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* cannot be handled. Halt execution and transfer control to debugger,
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* if one is attached.
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*/
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.org 0x200
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/* TLB refill, 32 bit task */
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uhi_mips_exception
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.org 0x280
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/* XTLB refill, 64 bit task */
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uhi_mips_exception
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.org 0x300
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/* Cache error exception */
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uhi_mips_exception
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.org 0x380
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/* General exception */
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uhi_mips_exception
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.org 0x400
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/* Catch interrupt exceptions */
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uhi_mips_exception
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.org 0x480
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/* EJTAG debug exception */
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1: b 1b
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nop
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.org 0x500
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#endif
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reset:
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#if __mips_isa_rev >= 6
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mfc0 t0, CP0_CONFIG, 5
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and t0, t0, MIPS_CONF5_VP
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beqz t0, 1f
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nop
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b 2f
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mfc0 t0, CP0_GLOBALNUMBER
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#endif
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#ifdef CONFIG_ARCH_BMIPS
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1: mfc0 t0, CP0_DIAGNOSTIC, 3
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and t0, t0, (1 << 31)
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#else
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1: mfc0 t0, CP0_EBASE
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and t0, t0, EBASE_CPUNUM
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#endif
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/* Hang if this isn't the first CPU in the system */
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2: beqz t0, 4f
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nop
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3: wait
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b 3b
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nop
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/* Init CP0 Status */
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4: mfc0 t0, CP0_STATUS
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and t0, ST0_IMPL
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or t0, ST0_BEV | ST0_ERL | STATUS_SET
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mtc0 t0, CP0_STATUS
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/*
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* Check whether CP0 Config1 is implemented. If not continue
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* with legacy Watch register initialization.
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*/
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mfc0 t0, CP0_CONFIG
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bgez t0, wr_legacy
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nop
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/*
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* Check WR bit in CP0 Config1 to determine if Watch registers
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* are implemented.
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*/
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mfc0 t0, CP0_CONFIG, 1
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andi t0, (1 << 3)
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beqz t0, wr_done
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nop
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/* Clear Watch Status bits and disable watch exceptions */
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li t1, 0x7 # Clear I, R and W conditions
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init_wr 0
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init_wr 1
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init_wr 2
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init_wr 3
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init_wr 4
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init_wr 5
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init_wr 6
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init_wr 7
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b wr_done
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nop
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wr_legacy:
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MTC0 zero, CP0_WATCHLO
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mtc0 zero, CP0_WATCHHI
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wr_done:
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/* Clear WP, IV and SW interrupts */
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mtc0 zero, CP0_CAUSE
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/* Clear timer interrupt (CP0_COUNT cleared on branch to 'reset') */
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mtc0 zero, CP0_COMPARE
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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mfc0 t0, CP0_CONFIG
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and t0, t0, MIPS_CONF_IMPL
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or t0, t0, CONF_CM_UNCACHED
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mtc0 t0, CP0_CONFIG
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ehb
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#endif
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#ifdef CONFIG_MIPS_CM
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PTR_LA t9, mips_cm_map
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jalr t9
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nop
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#endif
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#ifdef CONFIG_MIPS_INIT_STACK_IN_SRAM
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/* Set up initial stack and global data */
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setup_stack_gd
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# ifdef CONFIG_DEBUG_UART
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/* Earliest point to set up debug uart */
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PTR_LA t9, debug_uart_init
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jalr t9
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nop
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# endif
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#endif
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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# ifdef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* Initialize any external memory */
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PTR_LA t9, lowlevel_init
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jalr t9
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nop
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# endif
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/* Initialize caches... */
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PTR_LA t9, mips_cache_reset
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jalr t9
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nop
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# ifndef CONFIG_SYS_MIPS_CACHE_INIT_RAM_LOAD
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/* Initialize any external memory */
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PTR_LA t9, lowlevel_init
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jalr t9
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nop
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# endif
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#endif
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#ifndef CONFIG_MIPS_INIT_STACK_IN_SRAM
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/* Set up initial stack and global data */
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setup_stack_gd
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# ifdef CONFIG_DEBUG_UART
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/* Earliest point to set up debug uart */
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PTR_LA t9, debug_uart_init
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jalr t9
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nop
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# endif
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#endif
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move a0, zero # a0 <-- boot_flags = 0
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PTR_LA t9, board_init_f
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jr t9
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move ra, zero
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END(_start)
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