/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_SYSTEM_COUNTER_H
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#define _ASM_ARCH_SYSTEM_COUNTER_H
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/* System Counter */
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struct sctr_regs {
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u32 cntcr;
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u32 cntsr;
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u32 cntcv1;
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u32 cntcv2;
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u32 resv1[4];
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u32 cntfid0;
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u32 cntfid1;
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u32 cntfid2;
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u32 resv2[1001];
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u32 counterid[1];
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};
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#define SC_CNTCR_ENABLE (1 << 0)
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#define SC_CNTCR_HDBG (1 << 1)
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#define SC_CNTCR_FREQ0 (1 << 8)
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#define SC_CNTCR_FREQ1 (1 << 9)
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#endif
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