/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2022 Rockchip Electronics Co. Ltd.
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* Author: Joseph Chen <chenjh@rock-chips.com>
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*/
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#ifndef _ASM_ARCH_CRU_RK3528_H
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#define _ASM_ARCH_CRU_RK3528_H
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#define MHz 1000000
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#define KHz 1000
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#define OSC_HZ (24 * MHz)
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#define CPU_PVTPLL_HZ (1200 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ (1188 * MHz)
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#define CPLL_HZ (996 * MHz)
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#define PPLL_HZ (1000 * MHz)
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/* RK3528 pll id */
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enum rk3528_pll_id {
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APLL,
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CPLL,
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GPLL,
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PPLL,
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DPLL,
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PLL_COUNT,
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};
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struct rk3528_clk_info {
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unsigned long id;
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char *name;
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};
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struct rk3528_clk_priv {
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struct rk3528_cru *cru;
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struct rk3528_sysgrf *grf;
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ulong ppll_hz;
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ulong gpll_hz;
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ulong cpll_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rk3528_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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};
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struct rk3528_cru {
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uint32_t apll_con[5];
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uint32_t reserved0014[3];
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uint32_t cpll_con[5];
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uint32_t reserved0034[11];
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uint32_t gpll_con[5];
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uint32_t reserved0074[51+32];
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uint32_t reserved01c0[48];
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uint32_t mode_con[1];
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uint32_t reserved0284[31];
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uint32_t clksel_con[91];
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uint32_t reserved046c[229];
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uint32_t gate_con[46];
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uint32_t reserved08b8[82];
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uint32_t softrst_con[47];
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uint32_t reserved0abc[81];
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uint32_t glb_cnt_th;
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uint32_t glb_rst_st;
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uint32_t glb_srst_fst;
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uint32_t glb_srst_snd;
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uint32_t glb_rst_con;
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uint32_t reserved0c14[6];
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uint32_t corewfi_con;
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uint32_t reserved0c30[15604];
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/* pmucru */
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uint32_t reserved10000[192];
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uint32_t pmuclksel_con[3];
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uint32_t reserved1030c[317];
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uint32_t pmugate_con[3];
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uint32_t reserved1080c[125];
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uint32_t pmusoftrst_con[3];
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uint32_t reserved10a08[7550+8191];
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/* pciecru */
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uint32_t reserved20000[32];
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uint32_t ppll_con[5];
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uint32_t reserved20094[155];
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uint32_t pcieclksel_con[2];
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uint32_t reserved20308[318];
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uint32_t pciegate_con;
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};
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check_member(rk3528_cru, pciegate_con, 0x20800);
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struct rk3528_grf_clk_priv {
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struct rk3528_grf *grf;
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};
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struct pll_rate_table {
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unsigned long rate;
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unsigned int fbdiv;
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unsigned int postdiv1;
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unsigned int refdiv;
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unsigned int postdiv2;
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unsigned int dsmpd;
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unsigned int frac;
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};
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#define RK3528_PMU_CRU_BASE 0x10000
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#define RK3528_PCIE_CRU_BASE 0x20000
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#define RK3528_DDRPHY_CRU_BASE 0x28000
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#define RK3528_PLL_CON(x) ((x) * 0x4)
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#define RK3528_PCIE_PLL_CON(x) ((x) * 0x4 + RK3528_PCIE_CRU_BASE)
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#define RK3528_DDRPHY_PLL_CON(x) ((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
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#define RK3528_MODE_CON 0x280
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#define RK3528_CLKSEL_CON(x) ((x) * 0x4 + 0x300)
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#define RK3528_PMU_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
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#define RK3528_PCIE_CLKSEL_CON(x) ((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
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#define RK3528_DDRPHY_MODE_CON (0x280 + RK3528_DDRPHY_CRU_BASE)
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#define RK3528_DIV_ACLK_M_CORE_MASK 0x1f
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#define RK3528_DIV_ACLK_M_CORE_SHIFT 11
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#define RK3528_DIV_PCLK_DBG_MASK 0x1f
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#define RK3528_DIV_PCLK_DBG_SHIFT 1
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enum {
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/* CRU_CLKSEL_CON00 */
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CLK_MATRIX_50M_SRC_DIV_SHIFT = 2,
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CLK_MATRIX_50M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_50M_SRC_DIV_SHIFT,
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CLK_MATRIX_100M_SRC_DIV_SHIFT = 7,
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CLK_MATRIX_100M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_100M_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON01 */
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CLK_MATRIX_150M_SRC_DIV_SHIFT = 0,
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CLK_MATRIX_150M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_150M_SRC_DIV_SHIFT,
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CLK_MATRIX_200M_SRC_DIV_SHIFT = 5,
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CLK_MATRIX_200M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_200M_SRC_DIV_SHIFT,
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CLK_MATRIX_250M_SRC_DIV_SHIFT = 10,
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CLK_MATRIX_250M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_250M_SRC_DIV_SHIFT,
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CLK_MATRIX_250M_SRC_SEL_SHIFT = 15,
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CLK_MATRIX_250M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_250M_SRC_SEL_SHIFT,
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/* CRU_CLKSEL_CON02 */
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CLK_MATRIX_300M_SRC_DIV_SHIFT = 0,
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CLK_MATRIX_300M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_300M_SRC_DIV_SHIFT,
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CLK_MATRIX_339M_SRC_DIV_SHIFT = 5,
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CLK_MATRIX_339M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_339M_SRC_DIV_SHIFT,
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CLK_MATRIX_400M_SRC_DIV_SHIFT = 10,
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CLK_MATRIX_400M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_400M_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON03 */
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CLK_MATRIX_500M_SRC_DIV_SHIFT = 6,
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CLK_MATRIX_500M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_500M_SRC_DIV_SHIFT,
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CLK_MATRIX_500M_SRC_SEL_SHIFT = 11,
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CLK_MATRIX_500M_SRC_SEL_MASK = 0x1 << CLK_MATRIX_500M_SRC_SEL_SHIFT,
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/* CRU_CLKSEL_CON04 */
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CLK_MATRIX_600M_SRC_DIV_SHIFT = 0,
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CLK_MATRIX_600M_SRC_DIV_MASK = 0x1F << CLK_MATRIX_600M_SRC_DIV_SHIFT,
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CLK_MATRIX_250M_SRC_SEL_CLK_GPLL_MUX = 0U,
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CLK_MATRIX_250M_SRC_SEL_CLK_CPLL_MUX = 1U,
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CLK_MATRIX_500M_SRC_SEL_CLK_GPLL_MUX = 0U,
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CLK_MATRIX_500M_SRC_SEL_CLK_CPLL_MUX = 1U,
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/* PMUCRU_CLKSEL_CON00 */
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CLK_I2C2_SEL_SHIFT = 0,
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CLK_I2C2_SEL_MASK = 0x3 << CLK_I2C2_SEL_SHIFT,
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/* PCIE_CRU_CLKSEL_CON01 */
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PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT = 7,
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PCIE_CLK_MATRIX_50M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_50M_SRC_DIV_SHIFT,
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PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT = 11,
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PCIE_CLK_MATRIX_100M_SRC_DIV_MASK = 0x1f << PCIE_CLK_MATRIX_100M_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON32 */
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DCLK_VOP_SRC0_SEL_SHIFT = 10,
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DCLK_VOP_SRC0_SEL_MASK = 0x1 << DCLK_VOP_SRC0_SEL_SHIFT,
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DCLK_VOP_SRC0_DIV_SHIFT = 2,
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DCLK_VOP_SRC0_DIV_MASK = 0xFF << DCLK_VOP_SRC0_DIV_SHIFT,
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/* CRU_CLKSEL_CON33 */
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DCLK_VOP_SRC1_SEL_SHIFT = 8,
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DCLK_VOP_SRC1_SEL_MASK = 0x1 << DCLK_VOP_SRC1_SEL_SHIFT,
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DCLK_VOP_SRC1_DIV_SHIFT = 0,
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DCLK_VOP_SRC1_DIV_MASK = 0xFF << DCLK_VOP_SRC1_DIV_SHIFT,
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/* CRU_CLKSEL_CON43 */
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CLK_CORE_CRYPTO_SEL_SHIFT = 14,
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CLK_CORE_CRYPTO_SEL_MASK = 0x3 << CLK_CORE_CRYPTO_SEL_SHIFT,
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ACLK_BUS_VOPGL_ROOT_DIV_SHIFT = 0U,
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ACLK_BUS_VOPGL_ROOT_DIV_MASK = 0x7U << ACLK_BUS_VOPGL_ROOT_DIV_SHIFT,
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/* CRU_CLKSEL_CON44 */
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CLK_PWM0_SEL_SHIFT = 6,
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CLK_PWM0_SEL_MASK = 0x3 << CLK_PWM0_SEL_SHIFT,
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CLK_PWM1_SEL_SHIFT = 8,
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CLK_PWM1_SEL_MASK = 0x3 << CLK_PWM1_SEL_SHIFT,
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CLK_PWM0_SEL_CLK_MATRIX_100M_SRC = 0U,
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CLK_PWM0_SEL_CLK_MATRIX_50M_SRC = 1U,
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CLK_PWM0_SEL_XIN_OSC0_FUNC = 2U,
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CLK_PWM1_SEL_CLK_MATRIX_100M_SRC = 0U,
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CLK_PWM1_SEL_CLK_MATRIX_50M_SRC = 1U,
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CLK_PWM1_SEL_XIN_OSC0_FUNC = 2U,
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CLK_PKA_CRYPTO_SEL_SHIFT = 0,
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CLK_PKA_CRYPTO_SEL_MASK = 0x3 << CLK_PKA_CRYPTO_SEL_SHIFT,
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CLK_CORE_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
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CLK_CORE_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
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CLK_CORE_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
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CLK_CORE_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
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CLK_PKA_CRYPTO_SEL_CLK_MATRIX_300M_SRC = 0U,
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CLK_PKA_CRYPTO_SEL_CLK_MATRIX_200M_SRC = 1U,
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CLK_PKA_CRYPTO_SEL_CLK_MATRIX_100M_SRC = 2U,
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CLK_PKA_CRYPTO_SEL_XIN_OSC0_FUNC = 3U,
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/* CRU_CLKSEL_CON60 */
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CLK_MATRIX_25M_SRC_DIV_SHIFT = 2,
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CLK_MATRIX_25M_SRC_DIV_MASK = 0xff << CLK_MATRIX_25M_SRC_DIV_SHIFT,
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CLK_MATRIX_125M_SRC_DIV_SHIFT = 10,
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CLK_MATRIX_125M_SRC_DIV_MASK = 0x1f << CLK_MATRIX_125M_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON61 */
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SCLK_SFC_DIV_SHIFT = 6,
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SCLK_SFC_DIV_MASK = 0x3F << SCLK_SFC_DIV_SHIFT,
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SCLK_SFC_SEL_SHIFT = 12,
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SCLK_SFC_SEL_MASK = 0x3 << SCLK_SFC_SEL_SHIFT,
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SCLK_SFC_SEL_CLK_GPLL_MUX = 0U,
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SCLK_SFC_SEL_CLK_CPLL_MUX = 1U,
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SCLK_SFC_SEL_XIN_OSC0_FUNC = 2U,
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/* CRU_CLKSEL_CON62 */
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CCLK_SRC_EMMC_DIV_SHIFT = 0,
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CCLK_SRC_EMMC_DIV_MASK = 0x3F << CCLK_SRC_EMMC_DIV_SHIFT,
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CCLK_SRC_EMMC_SEL_SHIFT = 6,
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CCLK_SRC_EMMC_SEL_MASK = 0x3 << CCLK_SRC_EMMC_SEL_SHIFT,
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BCLK_EMMC_SEL_SHIFT = 8,
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BCLK_EMMC_SEL_MASK = 0x3 << BCLK_EMMC_SEL_SHIFT,
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/* CRU_CLKSEL_CON63 */
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CLK_I2C3_SEL_SHIFT = 12,
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CLK_I2C3_SEL_MASK = 0x3 << CLK_I2C3_SEL_SHIFT,
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CLK_I2C5_SEL_SHIFT = 14,
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CLK_I2C5_SEL_MASK = 0x3 << CLK_I2C5_SEL_SHIFT,
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CLK_SPI1_SEL_SHIFT = 10,
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CLK_SPI1_SEL_MASK = 0x3 << CLK_SPI1_SEL_SHIFT,
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/* CRU_CLKSEL_CON64 */
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CLK_I2C6_SEL_SHIFT = 0,
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CLK_I2C6_SEL_MASK = 0x3 << CLK_I2C6_SEL_SHIFT,
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/* CRU_CLKSEL_CON74 */
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CLK_SARADC_DIV_SHIFT = 0,
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CLK_SARADC_DIV_MASK = 0x7 << CLK_SARADC_DIV_SHIFT,
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CLK_TSADC_DIV_SHIFT = 3,
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CLK_TSADC_DIV_MASK = 0x1F << CLK_TSADC_DIV_SHIFT,
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CLK_TSADC_TSEN_DIV_SHIFT = 8,
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CLK_TSADC_TSEN_DIV_MASK = 0x1F << CLK_TSADC_TSEN_DIV_SHIFT,
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/* CRU_CLKSEL_CON79 */
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CLK_I2C1_SEL_SHIFT = 9,
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CLK_I2C1_SEL_MASK = 0x3 << CLK_I2C1_SEL_SHIFT,
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CLK_I2C0_SEL_SHIFT = 11,
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CLK_I2C0_SEL_MASK = 0x3 << CLK_I2C0_SEL_SHIFT,
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CLK_SPI0_SEL_SHIFT = 13,
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CLK_SPI0_SEL_MASK = 0x3 << CLK_SPI0_SEL_SHIFT,
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/* CRU_CLKSEL_CON83 */
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ACLK_VOP_ROOT_DIV_SHIFT = 12,
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ACLK_VOP_ROOT_DIV_MASK = 0x7 << ACLK_VOP_ROOT_DIV_SHIFT,
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ACLK_VOP_ROOT_SEL_SHIFT = 15,
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ACLK_VOP_ROOT_SEL_MASK = 0x1 << ACLK_VOP_ROOT_SEL_SHIFT,
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/* CRU_CLKSEL_CON84 */
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DCLK_VOP0_SEL_SHIFT = 0,
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DCLK_VOP0_SEL_MASK = 0x1 << DCLK_VOP0_SEL_SHIFT,
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DCLK_VOP_SRC_SEL_CLK_GPLL_MUX = 0U,
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DCLK_VOP_SRC_SEL_CLK_CPLL_MUX = 1U,
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ACLK_VOP_ROOT_SEL_CLK_GPLL_MUX = 0U,
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ACLK_VOP_ROOT_SEL_CLK_CPLL_MUX = 1U,
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DCLK_VOP0_SEL_DCLK_VOP_SRC0 = 0U,
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DCLK_VOP0_SEL_CLK_HDMIPHY_PIXEL_IO = 1U,
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/* CRU_CLKSEL_CON85 */
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CLK_I2C4_SEL_SHIFT = 13,
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CLK_I2C4_SEL_MASK = 0x3 << CLK_I2C4_SEL_SHIFT,
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CLK_I2C7_SEL_SHIFT = 0,
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CLK_I2C7_SEL_MASK = 0x3 << CLK_I2C7_SEL_SHIFT,
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CLK_I2C3_SEL_CLK_MATRIX_200M_SRC = 0U,
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CLK_I2C3_SEL_CLK_MATRIX_100M_SRC = 1U,
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CLK_I2C3_SEL_CLK_MATRIX_50M_SRC = 2U,
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CLK_I2C3_SEL_XIN_OSC0_FUNC = 3U,
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CLK_SPI1_SEL_CLK_MATRIX_200M_SRC = 0U,
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CLK_SPI1_SEL_CLK_MATRIX_100M_SRC = 1U,
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CLK_SPI1_SEL_CLK_MATRIX_50M_SRC = 2U,
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CLK_SPI1_SEL_XIN_OSC0_FUNC = 3U,
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CCLK_SRC_SDMMC0_DIV_SHIFT = 0,
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CCLK_SRC_SDMMC0_DIV_MASK = 0x3F << CCLK_SRC_SDMMC0_DIV_SHIFT,
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CCLK_SRC_SDMMC0_SEL_SHIFT = 6,
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CCLK_SRC_SDMMC0_SEL_MASK = 0x3 << CCLK_SRC_SDMMC0_SEL_SHIFT,
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CCLK_SRC_EMMC_SEL_CLK_GPLL_MUX = 0U,
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CCLK_SRC_EMMC_SEL_CLK_CPLL_MUX = 1U,
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CCLK_SRC_EMMC_SEL_XIN_OSC0_FUNC = 2U,
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BCLK_EMMC_SEL_CLK_MATRIX_200M_SRC = 0U,
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BCLK_EMMC_SEL_CLK_MATRIX_100M_SRC = 1U,
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BCLK_EMMC_SEL_CLK_MATRIX_50M_SRC = 2U,
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BCLK_EMMC_SEL_XIN_OSC0_FUNC = 3U,
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CCLK_SRC_SDMMC0_SEL_CLK_GPLL_MUX = 0U,
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CCLK_SRC_SDMMC0_SEL_CLK_CPLL_MUX = 1U,
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CCLK_SRC_SDMMC0_SEL_XIN_OSC0_FUNC = 2U,
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/* CRU_CLKSEL_CON04 */
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CLK_UART0_SRC_DIV_SHIFT = 5,
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CLK_UART0_SRC_DIV_MASK = 0x1F << CLK_UART0_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON05 */
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CLK_UART0_FRAC_DIV_SHIFT = 0,
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CLK_UART0_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART0_FRAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON06 */
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SCLK_UART0_SRC_SEL_SHIFT = 0,
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SCLK_UART0_SRC_SEL_MASK = 0x3 << SCLK_UART0_SRC_SEL_SHIFT,
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CLK_UART1_SRC_DIV_SHIFT = 2,
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CLK_UART1_SRC_DIV_MASK = 0x1F << CLK_UART1_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON07 */
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CLK_UART1_FRAC_DIV_SHIFT = 0,
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CLK_UART1_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART1_FRAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON08 */
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SCLK_UART1_SRC_SEL_SHIFT = 0,
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SCLK_UART1_SRC_SEL_MASK = 0x3 << SCLK_UART1_SRC_SEL_SHIFT,
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CLK_UART2_SRC_DIV_SHIFT = 2,
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CLK_UART2_SRC_DIV_MASK = 0x1F << CLK_UART2_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON09 */
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CLK_UART2_FRAC_DIV_SHIFT = 0,
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CLK_UART2_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART2_FRAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON10 */
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SCLK_UART2_SRC_SEL_SHIFT = 0,
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SCLK_UART2_SRC_SEL_MASK = 0x3 << SCLK_UART2_SRC_SEL_SHIFT,
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CLK_UART3_SRC_DIV_SHIFT = 2,
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CLK_UART3_SRC_DIV_MASK = 0x1F << CLK_UART3_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON11 */
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CLK_UART3_FRAC_DIV_SHIFT = 0,
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CLK_UART3_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART3_FRAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON12 */
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SCLK_UART3_SRC_SEL_SHIFT = 0,
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SCLK_UART3_SRC_SEL_MASK = 0x3 << SCLK_UART3_SRC_SEL_SHIFT,
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CLK_UART4_SRC_DIV_SHIFT = 2,
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CLK_UART4_SRC_DIV_MASK = 0x1F << CLK_UART4_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON13 */
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CLK_UART4_FRAC_DIV_SHIFT = 0,
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CLK_UART4_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART4_FRAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON14 */
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SCLK_UART4_SRC_SEL_SHIFT = 0,
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SCLK_UART4_SRC_SEL_MASK = 0x3 << SCLK_UART4_SRC_SEL_SHIFT,
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CLK_UART5_SRC_DIV_SHIFT = 2,
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CLK_UART5_SRC_DIV_MASK = 0x1F << CLK_UART5_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON15 */
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CLK_UART5_FRAC_DIV_SHIFT = 0,
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CLK_UART5_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART5_FRAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON16 */
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SCLK_UART5_SRC_SEL_SHIFT = 0,
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SCLK_UART5_SRC_SEL_MASK = 0x3 << SCLK_UART5_SRC_SEL_SHIFT,
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CLK_UART6_SRC_DIV_SHIFT = 2,
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CLK_UART6_SRC_DIV_MASK = 0x1F << CLK_UART6_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON17 */
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CLK_UART6_FRAC_DIV_SHIFT = 0,
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CLK_UART6_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART6_FRAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON18 */
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SCLK_UART6_SRC_SEL_SHIFT = 0,
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SCLK_UART6_SRC_SEL_MASK = 0x3 << SCLK_UART6_SRC_SEL_SHIFT,
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CLK_UART7_SRC_DIV_SHIFT = 2,
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CLK_UART7_SRC_DIV_MASK = 0x1F << CLK_UART7_SRC_DIV_SHIFT,
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/* CRU_CLKSEL_CON19 */
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CLK_UART7_FRAC_DIV_SHIFT = 0,
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CLK_UART7_FRAC_DIV_MASK = 0xFFFFFFFF << CLK_UART7_FRAC_DIV_SHIFT,
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/* CRU_CLKSEL_CON20 */
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SCLK_UART7_SRC_SEL_SHIFT = 0,
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SCLK_UART7_SRC_SEL_MASK = 0x3 << SCLK_UART7_SRC_SEL_SHIFT,
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SCLK_UART0_SRC_SEL_CLK_UART0_SRC = 0U,
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SCLK_UART0_SRC_SEL_CLK_UART0_FRAC = 1U,
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SCLK_UART0_SRC_SEL_XIN_OSC0_FUNC = 2U,
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/* CRU_CLKSEL_CON60 */
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CLK_GMAC1_VPU_25M_DIV_SHIFT = 2,
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CLK_GMAC1_VPU_25M_DIV_MASK = 0xFF << CLK_GMAC1_VPU_25M_DIV_SHIFT,
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/* CRU_CLKSEL_CON66 */
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CLK_GMAC1_SRC_VPU_DIV_SHIFT = 0,
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CLK_GMAC1_SRC_VPU_DIV_MASK = 0x3F << CLK_GMAC1_SRC_VPU_DIV_SHIFT,
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/* CRU_CLKSEL_CON84 */
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CLK_GMAC0_SRC_DIV_SHIFT = 3,
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CLK_GMAC0_SRC_DIV_MASK = 0x3F << CLK_GMAC0_SRC_DIV_SHIFT,
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};
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#endif
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