/*
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* (C) Copyright 2016 Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CRU_RK3328_H_
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#define __ASM_ARCH_CRU_RK3328_H_
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#include <common.h>
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struct rk3328_clk_priv {
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struct rk3328_cru *cru;
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ulong rate;
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ulong cpll_hz;
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ulong gpll_hz;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rk3328_cru {
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u32 apll_con[5];
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u32 reserved1[3];
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u32 dpll_con[5];
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u32 reserved2[3];
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u32 cpll_con[5];
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u32 reserved3[3];
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u32 gpll_con[5];
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u32 reserved4[3];
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u32 mode_con;
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u32 misc;
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u32 reserved5[2];
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u32 glb_cnt_th;
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u32 glb_rst_st;
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u32 glb_srst_snd_value;
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u32 glb_srst_fst_value;
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u32 npll_con[5];
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u32 reserved6[(0x100 - 0xb4) / 4];
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u32 clksel_con[53];
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u32 reserved7[(0x200 - 0x1d4) / 4];
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u32 clkgate_con[29];
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u32 reserved8[3];
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u32 ssgtbl[32];
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u32 softrst_con[12];
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u32 reserved9[(0x380 - 0x330) / 4];
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u32 sdmmc_con[2];
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u32 sdio_con[2];
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u32 emmc_con[2];
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u32 sdmmc_ext_con[2];
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};
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check_member(rk3328_cru, sdmmc_ext_con[1], 0x39c);
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/* PX30 pll id */
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enum rk3328_pll_id {
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APLL,
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DPLL,
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CPLL,
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GPLL,
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NPLL,
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PLL_COUNT,
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};
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struct rk3328_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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#define MHz 1000 * 1000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (600 * MHz)
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#define GPLL_HZ 491520000
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#define CPLL_HZ (1200 * MHz)
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#define ACLK_BUS_HZ (150 * MHz)
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#define ACLK_PERI_HZ (150 * MHz)
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#define PWM_CLOCK_HZ (74 * MHz)
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#define RK3328_PLL_CON(x) ((x) * 0x4)
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#define RK3328_CLKSEL_CON(x) ((x) * 0x4 + 0x100)
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#define RK3328_CLKGATE_CON(x) ((x) * 0x4 + 0x200)
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#define RK3328_MODE_CON 0x80
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enum {
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/* CLKSEL_CON0 */
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CLK_BUS_PLL_SEL_CPLL = 0,
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CLK_BUS_PLL_SEL_GPLL = 1,
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CLK_BUS_PLL_SEL_SHIFT = 13,
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CLK_BUS_PLL_SEL_MASK = 3 << CLK_BUS_PLL_SEL_SHIFT,
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ACLK_BUS_DIV_CON_SHIFT = 8,
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ACLK_BUS_DIV_CON_MASK = 0x1f << ACLK_BUS_DIV_CON_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 6,
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CORE_CLK_PLL_SEL_MASK = 3 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_GPLL,
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CORE_CLK_PLL_SEL_NPLL = 3,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x1f << CORE_DIV_CON_SHIFT,
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/* CLKSEL_CON1 */
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PCLK_BUS_DIV_CON_SHIFT = 12,
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PCLK_BUS_DIV_CON_MASK = 0x7 << PCLK_BUS_DIV_CON_SHIFT,
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HCLK_BUS_DIV_CON_SHIFT = 8,
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HCLK_BUS_DIV_CON_MASK = 0x3 << HCLK_BUS_DIV_CON_SHIFT,
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CORE_ACLK_DIV_SHIFT = 4,
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CORE_ACLK_DIV_MASK = 0x07 << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 0,
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CORE_DBG_DIV_MASK = 0x0f << CORE_DBG_DIV_SHIFT,
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/* CLKSEL_CON26 */
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GMAC2PHY_PLL_SEL_SHIFT = 7,
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GMAC2PHY_PLL_SEL_MASK = 1 << GMAC2PHY_PLL_SEL_SHIFT,
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GMAC2PHY_PLL_SEL_CPLL = 0,
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GMAC2PHY_PLL_SEL_GPLL = 1,
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GMAC2PHY_CLK_DIV_MASK = 0x1f,
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GMAC2PHY_CLK_DIV_SHIFT = 0,
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/* CLKSEL_CON27 */
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GMAC2IO_PLL_SEL_SHIFT = 7,
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GMAC2IO_PLL_SEL_MASK = 1 << GMAC2IO_PLL_SEL_SHIFT,
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GMAC2IO_PLL_SEL_CPLL = 0,
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GMAC2IO_PLL_SEL_GPLL = 1,
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GMAC2IO_CLK_DIV_MASK = 0x1f,
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GMAC2IO_CLK_DIV_SHIFT = 0,
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/* CLKSEL_CON28 */
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CLK_PERI_PLL_SEL_CPLL = 0,
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CLK_PERI_PLL_SEL_GPLL,
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CLK_PERI_PLL_SEL_HDMIPHY,
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CLK_PERI_PLL_SEL_SHIFT = 6,
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CLK_PERI_PLL_SEL_MASK = 3 << CLK_PERI_PLL_SEL_SHIFT,
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ACLK_PERI_DIV_CON_SHIFT = 0,
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ACLK_PERI_DIV_CON_MASK = 0x1f,
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/* CLKSEL_CON29 */
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PCLK_PERI_DIV_CON_SHIFT = 4,
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PCLK_PERI_DIV_CON_MASK = 0x7 << PCLK_PERI_DIV_CON_SHIFT,
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HCLK_PERI_DIV_CON_SHIFT = 0,
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HCLK_PERI_DIV_CON_MASK = 3 << HCLK_PERI_DIV_CON_SHIFT,
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/* CLKSEL_CON20 */
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CRYPTO_PLL_SEL_SHIFT = 7,
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CRYPTO_PLL_SEL_MASK = 0x1 << CRYPTO_PLL_SEL_SHIFT,
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CRYPTO_PLL_SEL_CPLL = 0,
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CRYPTO_PLL_SEL_GPLL,
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CRYPTO_DIV_SHIFT = 0,
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CRYPTO_DIV_MASK = 0x7f << CRYPTO_DIV_SHIFT,
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/* CLKSEL_CON22 */
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CLK_TSADC_DIV_CON_SHIFT = 0,
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CLK_TSADC_DIV_CON_MASK = 0x3ff,
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/* CLKSEL_CON23 */
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CLK_SARADC_DIV_CON_SHIFT = 0,
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CLK_SARADC_DIV_CON_MASK = GENMASK(9, 0),
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CLK_SARADC_DIV_CON_WIDTH = 10,
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/* CLKSEL_CON24 */
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CLK_PWM_PLL_SEL_CPLL = 0,
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CLK_PWM_PLL_SEL_GPLL,
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CLK_PWM_PLL_SEL_SHIFT = 15,
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CLK_PWM_PLL_SEL_MASK = 1 << CLK_PWM_PLL_SEL_SHIFT,
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CLK_PWM_DIV_CON_SHIFT = 8,
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CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
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CLK_SPI_PLL_SEL_CPLL = 0,
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CLK_SPI_PLL_SEL_GPLL,
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CLK_SPI_PLL_SEL_SHIFT = 7,
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CLK_SPI_PLL_SEL_MASK = 1 << CLK_SPI_PLL_SEL_SHIFT,
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CLK_SPI_DIV_CON_SHIFT = 0,
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CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
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/* CLKSEL_CON30 */
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CLK_SDMMC_PLL_SEL_CPLL = 0,
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CLK_SDMMC_PLL_SEL_GPLL,
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CLK_SDMMC_PLL_SEL_24M,
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CLK_SDMMC_PLL_SEL_USBPHY,
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CLK_SDMMC_PLL_SHIFT = 8,
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CLK_SDMMC_PLL_MASK = 0x3 << CLK_SDMMC_PLL_SHIFT,
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CLK_SDMMC_DIV_CON_SHIFT = 0,
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CLK_SDMMC_DIV_CON_MASK = 0xff << CLK_SDMMC_DIV_CON_SHIFT,
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/* CLKSEL_CON32 */
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CLK_EMMC_PLL_SEL_CPLL = 0,
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CLK_EMMC_PLL_SEL_GPLL,
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CLK_EMMC_PLL_SEL_24M,
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CLK_EMMC_PLL_SEL_USBPHY,
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CLK_EMMC_PLL_SHIFT = 8,
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CLK_EMMC_PLL_MASK = 0x3 << CLK_EMMC_PLL_SHIFT,
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CLK_EMMC_DIV_CON_SHIFT = 0,
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CLK_EMMC_DIV_CON_MASK = 0xff << CLK_EMMC_DIV_CON_SHIFT,
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/* CLKSEL_CON34 */
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CLK_I2C_PLL_SEL_CPLL = 0,
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CLK_I2C_PLL_SEL_GPLL,
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CLK_I2C_DIV_CON_MASK = 0x7f,
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CLK_I2C_PLL_SEL_MASK = 1,
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CLK_I2C1_PLL_SEL_SHIFT = 15,
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CLK_I2C1_DIV_CON_SHIFT = 8,
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CLK_I2C0_PLL_SEL_SHIFT = 7,
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CLK_I2C0_DIV_CON_SHIFT = 0,
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/* CLKSEL_CON35 */
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CLK_I2C3_PLL_SEL_SHIFT = 15,
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CLK_I2C3_DIV_CON_SHIFT = 8,
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CLK_I2C2_PLL_SEL_SHIFT = 7,
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CLK_I2C2_DIV_CON_SHIFT = 0,
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/* CRU_CLK_SEL37_CON */
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ACLK_VIO_PLL_SEL_CPLL = 0,
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ACLK_VIO_PLL_SEL_GPLL = 1,
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ACLK_VIO_PLL_SEL_HDMIPHY = 2,
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ACLK_VIO_PLL_SEL_USB480M = 3,
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ACLK_VIO_PLL_SEL_SHIFT = 6,
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ACLK_VIO_PLL_SEL_MASK = 3 << ACLK_VIO_PLL_SEL_SHIFT,
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ACLK_VIO_DIV_CON_SHIFT = 0,
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ACLK_VIO_DIV_CON_MASK = 0x1f << ACLK_VIO_DIV_CON_SHIFT,
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HCLK_VIO_DIV_CON_SHIFT = 8,
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HCLK_VIO_DIV_CON_MASK = 0x1f << HCLK_VIO_DIV_CON_SHIFT,
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/* CRU_CLK_SEL39_CON */
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ACLK_VOP_PLL_SEL_CPLL = 0,
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ACLK_VOP_PLL_SEL_GPLL = 1,
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ACLK_VOP_PLL_SEL_HDMIPHY = 2,
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ACLK_VOP_PLL_SEL_USB480M = 3,
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ACLK_VOP_PLL_SEL_SHIFT = 6,
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ACLK_VOP_PLL_SEL_MASK = 3 << ACLK_VOP_PLL_SEL_SHIFT,
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ACLK_VOP_DIV_CON_SHIFT = 0,
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ACLK_VOP_DIV_CON_MASK = 0x1f << ACLK_VOP_DIV_CON_SHIFT,
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/* CRU_CLK_SEL40_CON */
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DCLK_LCDC_PLL_SEL_GPLL = 0,
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DCLK_LCDC_PLL_SEL_CPLL = 1,
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DCLK_LCDC_PLL_SEL_SHIFT = 0,
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DCLK_LCDC_PLL_SEL_MASK = 1 << DCLK_LCDC_PLL_SEL_SHIFT,
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DCLK_LCDC_SEL_HDMIPHY = 0,
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DCLK_LCDC_SEL_PLL = 1,
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DCLK_LCDC_SEL_SHIFT = 1,
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DCLK_LCDC_SEL_MASK = 1 << DCLK_LCDC_SEL_SHIFT,
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DCLK_LCDC_DIV_CON_SHIFT = 8,
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DCLK_LCDC_DIV_CON_MASK = 0xFf << DCLK_LCDC_DIV_CON_SHIFT,
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};
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#endif /* __ASM_ARCH_CRU_RK3328_H_ */
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