/*
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* (C) Copyright 2016 Heiko Stuebner <heiko@sntech.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_ARCH_CRU_RK3066_H
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#define _ASM_ARCH_CRU_RK3066_H
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_HZ (1416 * 1000000)
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#define APLL_SAFE_HZ (600 * 1000000)
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#define GPLL_HZ (594 * 1000000)
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#define CPLL_HZ (384 * 1000000)
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/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */
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#define CPU_ACLK_HZ 297000000
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#define CPU_HCLK_HZ 148500000
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#define CPU_PCLK_HZ 74250000
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#define CPU_H2P_HZ 74250000
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#define PERI_ACLK_HZ 148500000
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#define PERI_HCLK_HZ 148500000
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#define PERI_PCLK_HZ 74250000
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk3066_clk_priv {
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struct rk3066_grf *grf;
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struct rk3066_cru *cru;
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ulong rate;
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bool has_bwadj;
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ulong armclk_hz;
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ulong armclk_enter_hz;
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ulong armclk_init_hz;
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bool sync_kernel;
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bool set_armclk_rate;
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};
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struct rk3066_cru {
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struct rk3066_pll {
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u32 con0;
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u32 con1;
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u32 con2;
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u32 con3;
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} pll[4];
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u32 cru_mode_con;
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u32 cru_clksel_con[35];
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u32 cru_clkgate_con[10];
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u32 reserved1[2];
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u32 cru_glb_srst_fst_value;
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u32 cru_glb_srst_snd_value;
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u32 reserved2[2];
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u32 cru_softrst_con[9];
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u32 cru_misc_con;
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u32 reserved3[2];
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u32 cru_glb_cnt_th;
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};
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check_member(rk3066_cru, cru_glb_cnt_th, 0x0140);
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struct rk3066_clk_info {
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unsigned long id;
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char *name;
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bool is_cru;
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};
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/* CRU_CLKSEL0_CON */
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enum {
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/* a9_core_div: core = core_src / (a9_core_div + 1) */
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A9_CORE_DIV_SHIFT = 9,
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A9_CORE_DIV_MASK = 0x1f << A9_CORE_DIV_SHIFT,
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CORE_PLL_SHIFT = 8,
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CORE_PLL_MASK = 1 << CORE_PLL_SHIFT,
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CORE_PLL_SELECT_APLL = 0,
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CORE_PLL_SELECT_GPLL,
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/* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */
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CORE_PERI_DIV_SHIFT = 6,
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CORE_PERI_DIV_MASK = 3 << CORE_PERI_DIV_SHIFT,
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/* aclk_cpu pll selection */
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CPU_ACLK_PLL_SHIFT = 5,
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CPU_ACLK_PLL_MASK = 1 << CPU_ACLK_PLL_SHIFT,
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CPU_ACLK_PLL_SELECT_APLL = 0,
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CPU_ACLK_PLL_SELECT_GPLL,
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/* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */
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A9_CPU_DIV_SHIFT = 0,
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A9_CPU_DIV_MASK = 0x1f << A9_CPU_DIV_SHIFT,
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};
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/* CRU_CLKSEL1_CON */
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enum {
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/* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */
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AHB2APB_DIV_SHIFT = 14,
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AHB2APB_DIV_MASK = 3 << AHB2APB_DIV_SHIFT,
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/* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */
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CPU_PCLK_DIV_SHIFT = 12,
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CPU_PCLK_DIV_MASK = 3 << CPU_PCLK_DIV_SHIFT,
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/* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */
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CPU_HCLK_DIV_SHIFT = 8,
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CPU_HCLK_DIV_MASK = 3 << CPU_HCLK_DIV_SHIFT,
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/* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */
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CORE_ACLK_DIV_SHIFT = 3,
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CORE_ACLK_DIV_MASK = 7 << CORE_ACLK_DIV_SHIFT,
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};
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/* CRU_CLKSEL10_CON */
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enum {
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PERI_SEL_PLL_SHIFT = 15,
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PERI_SEL_PLL_MASK = 1 << PERI_SEL_PLL_SHIFT,
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PERI_SEL_CPLL = 0,
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PERI_SEL_GPLL,
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/* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */
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PERI_PCLK_DIV_SHIFT = 12,
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PERI_PCLK_DIV_MASK = 3 << PERI_PCLK_DIV_SHIFT,
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/* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */
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PERI_HCLK_DIV_SHIFT = 8,
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PERI_HCLK_DIV_MASK = 3 << PERI_HCLK_DIV_SHIFT,
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/* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */
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PERI_ACLK_DIV_SHIFT = 0,
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PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
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};
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/* CRU_CLKSEL11_CON */
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enum {
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MMC0_DIV_SHIFT = 0,
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MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
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};
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/* CRU_CLKSEL12_CON */
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enum {
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UART_PLL_SHIFT = 15,
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UART_PLL_MASK = 1 << UART_PLL_SHIFT,
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UART_PLL_SELECT_GENERAL = 0,
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UART_PLL_SELECT_CODEC,
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EMMC_DIV_SHIFT = 8,
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EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
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SDIO_DIV_SHIFT = 0,
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SDIO_DIV_MASK = 0x3f << SDIO_DIV_SHIFT,
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};
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/* CRU_CLKSEL25_CON */
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enum {
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SPI1_DIV_SHIFT = 8,
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SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT,
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SPI0_DIV_SHIFT = 0,
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SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT,
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};
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/* CRU_MODE_CON */
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enum {
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GPLL_MODE_SHIFT = 12,
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GPLL_MODE_MASK = 3 << GPLL_MODE_SHIFT,
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GPLL_MODE_SLOW = 0,
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GPLL_MODE_NORMAL,
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GPLL_MODE_DEEP,
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CPLL_MODE_SHIFT = 8,
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CPLL_MODE_MASK = 3 << CPLL_MODE_SHIFT,
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CPLL_MODE_SLOW = 0,
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CPLL_MODE_NORMAL,
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CPLL_MODE_DEEP,
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DPLL_MODE_SHIFT = 4,
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DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
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DPLL_MODE_SLOW = 0,
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DPLL_MODE_NORMAL,
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DPLL_MODE_DEEP,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
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APLL_MODE_SLOW = 0,
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APLL_MODE_NORMAL,
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APLL_MODE_DEEP,
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};
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/* CRU_APLL_CON0 */
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enum {
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CLKR_SHIFT = 8,
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CLKR_MASK = 0x3f << CLKR_SHIFT,
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CLKOD_SHIFT = 0,
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CLKOD_MASK = 0x3f << CLKOD_SHIFT,
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};
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/* CRU_APLL_CON1 */
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enum {
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CLKF_SHIFT = 0,
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CLKF_MASK = 0x1fff << CLKF_SHIFT,
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};
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#endif
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