/*
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* (C) Copyright 2012
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* eInfochips Ltd. <www.einfochips.com>
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* Written-by: Ajay Bhargav <contact@8051projects.net>
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*
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* (C) Copyright 2009
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* Marvell Semiconductor <www.marvell.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __UTMI_ARMADA100__
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#define __UTMI_ARMADA100__
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#define UTMI_PHY_BASE 0xD4206000
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/* utmi_ctrl - bits */
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#define INPKT_DELAY_SOF (1 << 28)
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#define PLL_PWR_UP 2
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#define PHY_PWR_UP 1
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/* utmi_pll - bits */
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#define PLL_FBDIV_MASK 0x00000FF0
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#define PLL_FBDIV 4
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#define PLL_REFDIV_MASK 0x0000000F
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#define PLL_REFDIV 0
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#define PLL_READY 0x800000
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#define VCOCAL_START (1 << 21)
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#define N_DIVIDER 0xEE
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#define M_DIVIDER 0x0B
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/* utmi_tx - bits */
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#define CK60_PHSEL 17
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#define PHSEL_VAL 0x4
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#define RCAL_START (1 << 12)
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/*
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* USB PHY registers
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* Refer Datasheet Appendix A.21
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*/
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struct armd1usb_phy_reg {
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u32 utmi_rev; /* USB PHY Revision */
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u32 utmi_ctrl; /* USB PHY Control register */
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u32 utmi_pll; /* PLL register */
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u32 utmi_tx; /* Tx register */
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u32 utmi_rx; /* Rx register */
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u32 utmi_ivref; /* IVREF register */
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u32 utmi_tst_g0; /* Test group 0 register */
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u32 utmi_tst_g1; /* Test group 1 register */
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u32 utmi_tst_g2; /* Test group 2 register */
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u32 utmi_tst_g3; /* Test group 3 register */
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u32 utmi_tst_g4; /* Test group 4 register */
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u32 utmi_tst_g5; /* Test group 5 register */
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u32 utmi_reserve; /* Reserve Register */
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u32 utmi_usb_int; /* USB interuppt register */
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u32 utmi_dbg_ctl; /* Debug control register */
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u32 utmi_otg_addon; /* OTG addon register */
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};
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int utmi_init(void);
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#endif /* __UTMI_ARMADA100__ */
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