/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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*
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* Header file containing the public API for the System Controller (SC)
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* Power Management (PM) function. This includes functions for power state
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* control, clock control, reset control, and wake-up event control.
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*
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* PM_SVC (SVC) Power Management Service
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*
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* Module for the Power Management (PM) service.
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*/
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#ifndef _SC_PM_API_H
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#define _SC_PM_API_H
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#include <linux/firmware/imx/sci.h>
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/*
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* This type is used to indicate RPC PM function calls.
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*/
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enum imx_sc_pm_func {
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IMX_SC_PM_FUNC_UNKNOWN = 0,
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IMX_SC_PM_FUNC_SET_SYS_POWER_MODE = 19,
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IMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE = 1,
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IMX_SC_PM_FUNC_GET_SYS_POWER_MODE = 2,
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IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE = 3,
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IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE = 4,
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IMX_SC_PM_FUNC_REQ_LOW_POWER_MODE = 16,
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IMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR = 17,
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IMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE = 18,
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IMX_SC_PM_FUNC_SET_CLOCK_RATE = 5,
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IMX_SC_PM_FUNC_GET_CLOCK_RATE = 6,
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IMX_SC_PM_FUNC_CLOCK_ENABLE = 7,
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IMX_SC_PM_FUNC_SET_CLOCK_PARENT = 14,
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IMX_SC_PM_FUNC_GET_CLOCK_PARENT = 15,
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IMX_SC_PM_FUNC_RESET = 13,
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IMX_SC_PM_FUNC_RESET_REASON = 10,
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IMX_SC_PM_FUNC_BOOT = 8,
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IMX_SC_PM_FUNC_REBOOT = 9,
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IMX_SC_PM_FUNC_REBOOT_PARTITION = 12,
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IMX_SC_PM_FUNC_CPU_START = 11,
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};
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/*
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* Defines for ALL parameters
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*/
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#define IMX_SC_PM_CLK_ALL UINT8_MAX /* All clocks */
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/*
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* Defines for SC PM Power Mode
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*/
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#define IMX_SC_PM_PW_MODE_OFF 0 /* Power off */
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#define IMX_SC_PM_PW_MODE_STBY 1 /* Power in standby */
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#define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */
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#define IMX_SC_PM_PW_MODE_ON 3 /* Power on */
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/*
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* Defines for SC PM CLK
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*/
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#define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */
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#define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */
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#define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */
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#define IMX_SC_PM_CLK_PHY 3 /* Phy clock */
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#define IMX_SC_PM_CLK_MISC 4 /* Misc clock */
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#define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */
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#define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */
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#define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */
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#define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */
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#define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */
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#define IMX_SC_PM_CLK_CPU 2 /* CPU clock */
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#define IMX_SC_PM_CLK_PLL 4 /* PLL */
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#define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */
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/*
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* Defines for SC PM CLK Parent
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*/
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#define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */
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#define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */
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#define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */
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#define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */
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#define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */
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#endif /* _SC_PM_API_H */
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