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| /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
| #ifndef __DT_BINDINGS_POWER_RK1808_POWER_H__
| #define __DT_BINDINGS_POWER_RK1808_POWER_H__
|
| /* VD_CORE */
| #define RK1808_PD_A35_0 0
| #define RK1808_PD_A35_1 1
| #define RK1808_PD_SCU 2
| #define RK1808_VD_CORE 3
|
| /* VD_NPU */
| #define RK1808_VD_NPU 4
|
| /* VD_LOGIC */
| #define RK1808_PD_DDR 5
| #define RK1808_PD_PCIE 6
| #define RK1808_PD_VPU 7
| #define RK1808_PD_VIO 8
|
| #endif
|
|
