/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* HDMI driver definition for TI OMAP5 processors.
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*
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* Copyright (C) 2011-2012 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef _HDMI5_CORE_H_
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#define _HDMI5_CORE_H_
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#include "hdmi.h"
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/* HDMI IP Core System */
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/* HDMI Identification */
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#define HDMI_CORE_DESIGN_ID 0x00000
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#define HDMI_CORE_REVISION_ID 0x00004
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#define HDMI_CORE_PRODUCT_ID0 0x00008
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#define HDMI_CORE_PRODUCT_ID1 0x0000C
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#define HDMI_CORE_CONFIG0_ID 0x00010
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#define HDMI_CORE_CONFIG1_ID 0x00014
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#define HDMI_CORE_CONFIG2_ID 0x00018
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#define HDMI_CORE_CONFIG3_ID 0x0001C
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/* HDMI Interrupt */
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#define HDMI_CORE_IH_FC_STAT0 0x00400
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#define HDMI_CORE_IH_FC_STAT1 0x00404
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#define HDMI_CORE_IH_FC_STAT2 0x00408
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#define HDMI_CORE_IH_AS_STAT0 0x0040C
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#define HDMI_CORE_IH_PHY_STAT0 0x00410
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#define HDMI_CORE_IH_I2CM_STAT0 0x00414
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#define HDMI_CORE_IH_CEC_STAT0 0x00418
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#define HDMI_CORE_IH_VP_STAT0 0x0041C
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#define HDMI_CORE_IH_I2CMPHY_STAT0 0x00420
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#define HDMI_CORE_IH_MUTE 0x007FC
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/* HDMI Video Sampler */
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#define HDMI_CORE_TX_INVID0 0x00800
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#define HDMI_CORE_TX_INSTUFFING 0x00804
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#define HDMI_CORE_TX_RGYDATA0 0x00808
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#define HDMI_CORE_TX_RGYDATA1 0x0080C
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#define HDMI_CORE_TX_RCRDATA0 0x00810
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#define HDMI_CORE_TX_RCRDATA1 0x00814
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#define HDMI_CORE_TX_BCBDATA0 0x00818
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#define HDMI_CORE_TX_BCBDATA1 0x0081C
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/* HDMI Video Packetizer */
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#define HDMI_CORE_VP_STATUS 0x02000
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#define HDMI_CORE_VP_PR_CD 0x02004
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#define HDMI_CORE_VP_STUFF 0x02008
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#define HDMI_CORE_VP_REMAP 0x0200C
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#define HDMI_CORE_VP_CONF 0x02010
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#define HDMI_CORE_VP_STAT 0x02014
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#define HDMI_CORE_VP_INT 0x02018
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#define HDMI_CORE_VP_MASK 0x0201C
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#define HDMI_CORE_VP_POL 0x02020
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/* Frame Composer */
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#define HDMI_CORE_FC_INVIDCONF 0x04000
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#define HDMI_CORE_FC_INHACTIV0 0x04004
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#define HDMI_CORE_FC_INHACTIV1 0x04008
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#define HDMI_CORE_FC_INHBLANK0 0x0400C
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#define HDMI_CORE_FC_INHBLANK1 0x04010
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#define HDMI_CORE_FC_INVACTIV0 0x04014
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#define HDMI_CORE_FC_INVACTIV1 0x04018
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#define HDMI_CORE_FC_INVBLANK 0x0401C
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#define HDMI_CORE_FC_HSYNCINDELAY0 0x04020
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#define HDMI_CORE_FC_HSYNCINDELAY1 0x04024
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#define HDMI_CORE_FC_HSYNCINWIDTH0 0x04028
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#define HDMI_CORE_FC_HSYNCINWIDTH1 0x0402C
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#define HDMI_CORE_FC_VSYNCINDELAY 0x04030
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#define HDMI_CORE_FC_VSYNCINWIDTH 0x04034
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#define HDMI_CORE_FC_INFREQ0 0x04038
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#define HDMI_CORE_FC_INFREQ1 0x0403C
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#define HDMI_CORE_FC_INFREQ2 0x04040
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#define HDMI_CORE_FC_CTRLDUR 0x04044
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#define HDMI_CORE_FC_EXCTRLDUR 0x04048
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#define HDMI_CORE_FC_EXCTRLSPAC 0x0404C
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#define HDMI_CORE_FC_CH0PREAM 0x04050
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#define HDMI_CORE_FC_CH1PREAM 0x04054
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#define HDMI_CORE_FC_CH2PREAM 0x04058
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#define HDMI_CORE_FC_AVICONF3 0x0405C
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#define HDMI_CORE_FC_GCP 0x04060
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#define HDMI_CORE_FC_AVICONF0 0x04064
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#define HDMI_CORE_FC_AVICONF1 0x04068
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#define HDMI_CORE_FC_AVICONF2 0x0406C
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#define HDMI_CORE_FC_AVIVID 0x04070
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#define HDMI_CORE_FC_AVIETB0 0x04074
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#define HDMI_CORE_FC_AVIETB1 0x04078
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#define HDMI_CORE_FC_AVISBB0 0x0407C
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#define HDMI_CORE_FC_AVISBB1 0x04080
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#define HDMI_CORE_FC_AVIELB0 0x04084
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#define HDMI_CORE_FC_AVIELB1 0x04088
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#define HDMI_CORE_FC_AVISRB0 0x0408C
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#define HDMI_CORE_FC_AVISRB1 0x04090
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#define HDMI_CORE_FC_AUDICONF0 0x04094
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#define HDMI_CORE_FC_AUDICONF1 0x04098
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#define HDMI_CORE_FC_AUDICONF2 0x0409C
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#define HDMI_CORE_FC_AUDICONF3 0x040A0
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#define HDMI_CORE_FC_VSDIEEEID0 0x040A4
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#define HDMI_CORE_FC_VSDSIZE 0x040A8
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#define HDMI_CORE_FC_VSDIEEEID1 0x040C0
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#define HDMI_CORE_FC_VSDIEEEID2 0x040C4
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#define HDMI_CORE_FC_VSDPAYLOAD(n) (n * 4 + 0x040C8)
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#define HDMI_CORE_FC_SPDVENDORNAME(n) (n * 4 + 0x04128)
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#define HDMI_CORE_FC_SPDPRODUCTNAME(n) (n * 4 + 0x04148)
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#define HDMI_CORE_FC_SPDDEVICEINF 0x04188
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#define HDMI_CORE_FC_AUDSCONF 0x0418C
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#define HDMI_CORE_FC_AUDSSTAT 0x04190
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#define HDMI_CORE_FC_AUDSV 0x04194
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#define HDMI_CORE_FC_AUDSU 0x04198
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#define HDMI_CORE_FC_AUDSCHNLS(n) (n * 4 + 0x0419C)
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#define HDMI_CORE_FC_CTRLQHIGH 0x041CC
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#define HDMI_CORE_FC_CTRLQLOW 0x041D0
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#define HDMI_CORE_FC_ACP0 0x041D4
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#define HDMI_CORE_FC_ACP(n) ((16-n) * 4 + 0x04208)
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#define HDMI_CORE_FC_ISCR1_0 0x04248
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#define HDMI_CORE_FC_ISCR1(n) ((16-n) * 4 + 0x0424C)
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#define HDMI_CORE_FC_ISCR2(n) ((15-n) * 4 + 0x0428C)
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#define HDMI_CORE_FC_DATAUTO0 0x042CC
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#define HDMI_CORE_FC_DATAUTO1 0x042D0
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#define HDMI_CORE_FC_DATAUTO2 0x042D4
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#define HDMI_CORE_FC_DATMAN 0x042D8
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#define HDMI_CORE_FC_DATAUTO3 0x042DC
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#define HDMI_CORE_FC_RDRB(n) (n * 4 + 0x042E0)
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#define HDMI_CORE_FC_STAT0 0x04340
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#define HDMI_CORE_FC_INT0 0x04344
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#define HDMI_CORE_FC_MASK0 0x04348
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#define HDMI_CORE_FC_POL0 0x0434C
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#define HDMI_CORE_FC_STAT1 0x04350
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#define HDMI_CORE_FC_INT1 0x04354
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#define HDMI_CORE_FC_MASK1 0x04358
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#define HDMI_CORE_FC_POL1 0x0435C
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#define HDMI_CORE_FC_STAT2 0x04360
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#define HDMI_CORE_FC_INT2 0x04364
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#define HDMI_CORE_FC_MASK2 0x04368
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#define HDMI_CORE_FC_POL2 0x0436C
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#define HDMI_CORE_FC_PRCONF 0x04380
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#define HDMI_CORE_FC_GMD_STAT 0x04400
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#define HDMI_CORE_FC_GMD_EN 0x04404
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#define HDMI_CORE_FC_GMD_UP 0x04408
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#define HDMI_CORE_FC_GMD_CONF 0x0440C
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#define HDMI_CORE_FC_GMD_HB 0x04410
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#define HDMI_CORE_FC_GMD_PB(n) (n * 4 + 0x04414)
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#define HDMI_CORE_FC_DBGFORCE 0x04800
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#define HDMI_CORE_FC_DBGAUD0CH0 0x04804
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#define HDMI_CORE_FC_DBGAUD1CH0 0x04808
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#define HDMI_CORE_FC_DBGAUD2CH0 0x0480C
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#define HDMI_CORE_FC_DBGAUD0CH1 0x04810
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#define HDMI_CORE_FC_DBGAUD1CH1 0x04814
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#define HDMI_CORE_FC_DBGAUD2CH1 0x04818
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#define HDMI_CORE_FC_DBGAUD0CH2 0x0481C
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#define HDMI_CORE_FC_DBGAUD1CH2 0x04820
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#define HDMI_CORE_FC_DBGAUD2CH2 0x04824
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#define HDMI_CORE_FC_DBGAUD0CH3 0x04828
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#define HDMI_CORE_FC_DBGAUD1CH3 0x0482C
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#define HDMI_CORE_FC_DBGAUD2CH3 0x04830
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#define HDMI_CORE_FC_DBGAUD0CH4 0x04834
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#define HDMI_CORE_FC_DBGAUD1CH4 0x04838
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#define HDMI_CORE_FC_DBGAUD2CH4 0x0483C
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#define HDMI_CORE_FC_DBGAUD0CH5 0x04840
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#define HDMI_CORE_FC_DBGAUD1CH5 0x04844
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#define HDMI_CORE_FC_DBGAUD2CH5 0x04848
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#define HDMI_CORE_FC_DBGAUD0CH6 0x0484C
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#define HDMI_CORE_FC_DBGAUD1CH6 0x04850
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#define HDMI_CORE_FC_DBGAUD2CH6 0x04854
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#define HDMI_CORE_FC_DBGAUD0CH7 0x04858
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#define HDMI_CORE_FC_DBGAUD1CH7 0x0485C
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#define HDMI_CORE_FC_DBGAUD2CH7 0x04860
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#define HDMI_CORE_FC_DBGTMDS0 0x04864
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#define HDMI_CORE_FC_DBGTMDS1 0x04868
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#define HDMI_CORE_FC_DBGTMDS2 0x0486C
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#define HDMI_CORE_PHY_MASK0 0x0C018
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#define HDMI_CORE_PHY_I2CM_INT_ADDR 0x0C09C
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#define HDMI_CORE_PHY_I2CM_CTLINT_ADDR 0x0C0A0
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/* HDMI Audio */
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#define HDMI_CORE_AUD_CONF0 0x0C400
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#define HDMI_CORE_AUD_CONF1 0x0C404
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#define HDMI_CORE_AUD_INT 0x0C408
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#define HDMI_CORE_AUD_N1 0x0C800
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#define HDMI_CORE_AUD_N2 0x0C804
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#define HDMI_CORE_AUD_N3 0x0C808
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#define HDMI_CORE_AUD_CTS1 0x0C80C
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#define HDMI_CORE_AUD_CTS2 0x0C810
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#define HDMI_CORE_AUD_CTS3 0x0C814
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#define HDMI_CORE_AUD_INCLKFS 0x0C818
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#define HDMI_CORE_AUD_CC08 0x0CC08
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#define HDMI_CORE_AUD_GP_CONF0 0x0D400
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#define HDMI_CORE_AUD_GP_CONF1 0x0D404
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#define HDMI_CORE_AUD_GP_CONF2 0x0D408
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#define HDMI_CORE_AUD_D010 0x0D010
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#define HDMI_CORE_AUD_GP_STAT 0x0D40C
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#define HDMI_CORE_AUD_GP_INT 0x0D410
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#define HDMI_CORE_AUD_GP_POL 0x0D414
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#define HDMI_CORE_AUD_GP_MASK 0x0D418
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/* HDMI Main Controller */
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#define HDMI_CORE_MC_CLKDIS 0x10004
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#define HDMI_CORE_MC_SWRSTZREQ 0x10008
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#define HDMI_CORE_MC_FLOWCTRL 0x10010
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#define HDMI_CORE_MC_PHYRSTZ 0x10014
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#define HDMI_CORE_MC_LOCKONCLOCK 0x10018
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/* HDMI COLOR SPACE CONVERTER */
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#define HDMI_CORE_CSC_CFG 0x10400
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#define HDMI_CORE_CSC_SCALE 0x10404
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#define HDMI_CORE_CSC_COEF_A1_MSB 0x10408
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#define HDMI_CORE_CSC_COEF_A1_LSB 0x1040C
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#define HDMI_CORE_CSC_COEF_A2_MSB 0x10410
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#define HDMI_CORE_CSC_COEF_A2_LSB 0x10414
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#define HDMI_CORE_CSC_COEF_A3_MSB 0x10418
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#define HDMI_CORE_CSC_COEF_A3_LSB 0x1041C
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#define HDMI_CORE_CSC_COEF_A4_MSB 0x10420
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#define HDMI_CORE_CSC_COEF_A4_LSB 0x10424
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#define HDMI_CORE_CSC_COEF_B1_MSB 0x10428
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#define HDMI_CORE_CSC_COEF_B1_LSB 0x1042C
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#define HDMI_CORE_CSC_COEF_B2_MSB 0x10430
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#define HDMI_CORE_CSC_COEF_B2_LSB 0x10434
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#define HDMI_CORE_CSC_COEF_B3_MSB 0x10438
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#define HDMI_CORE_CSC_COEF_B3_LSB 0x1043C
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#define HDMI_CORE_CSC_COEF_B4_MSB 0x10440
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#define HDMI_CORE_CSC_COEF_B4_LSB 0x10444
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#define HDMI_CORE_CSC_COEF_C1_MSB 0x10448
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#define HDMI_CORE_CSC_COEF_C1_LSB 0x1044C
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#define HDMI_CORE_CSC_COEF_C2_MSB 0x10450
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#define HDMI_CORE_CSC_COEF_C2_LSB 0x10454
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#define HDMI_CORE_CSC_COEF_C3_MSB 0x10458
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#define HDMI_CORE_CSC_COEF_C3_LSB 0x1045C
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#define HDMI_CORE_CSC_COEF_C4_MSB 0x10460
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#define HDMI_CORE_CSC_COEF_C4_LSB 0x10464
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/* HDMI HDCP */
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#define HDMI_CORE_HDCP_MASK 0x14020
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/* HDMI CEC */
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#define HDMI_CORE_CEC_MASK 0x17408
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/* HDMI I2C Master */
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#define HDMI_CORE_I2CM_SLAVE 0x157C8
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#define HDMI_CORE_I2CM_ADDRESS 0x157CC
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#define HDMI_CORE_I2CM_DATAO 0x157D0
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#define HDMI_CORE_I2CM_DATAI 0X157D4
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#define HDMI_CORE_I2CM_OPERATION 0x157D8
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#define HDMI_CORE_I2CM_INT 0x157DC
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#define HDMI_CORE_I2CM_CTLINT 0x157E0
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#define HDMI_CORE_I2CM_DIV 0x157E4
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#define HDMI_CORE_I2CM_SEGADDR 0x157E8
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#define HDMI_CORE_I2CM_SOFTRSTZ 0x157EC
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#define HDMI_CORE_I2CM_SEGPTR 0x157F0
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#define HDMI_CORE_I2CM_SS_SCL_HCNT_1_ADDR 0x157F4
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#define HDMI_CORE_I2CM_SS_SCL_HCNT_0_ADDR 0x157F8
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#define HDMI_CORE_I2CM_SS_SCL_LCNT_1_ADDR 0x157FC
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#define HDMI_CORE_I2CM_SS_SCL_LCNT_0_ADDR 0x15800
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#define HDMI_CORE_I2CM_FS_SCL_HCNT_1_ADDR 0x15804
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#define HDMI_CORE_I2CM_FS_SCL_HCNT_0_ADDR 0x15808
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#define HDMI_CORE_I2CM_FS_SCL_LCNT_1_ADDR 0x1580C
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#define HDMI_CORE_I2CM_FS_SCL_LCNT_0_ADDR 0x15810
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#define HDMI_CORE_I2CM_SDA_HOLD_ADDR 0x15814
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enum hdmi_core_packet_mode {
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HDMI_PACKETMODERESERVEDVALUE = 0,
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HDMI_PACKETMODE24BITPERPIXEL = 4,
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HDMI_PACKETMODE30BITPERPIXEL = 5,
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HDMI_PACKETMODE36BITPERPIXEL = 6,
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HDMI_PACKETMODE48BITPERPIXEL = 7,
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};
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struct hdmi_core_vid_config {
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struct hdmi_config v_fc_config;
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enum hdmi_core_packet_mode packet_mode;
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int data_enable_pol;
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int vblank_osc;
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int hblank;
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int vblank;
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};
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struct csc_table {
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u16 a1, a2, a3, a4;
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u16 b1, b2, b3, b4;
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u16 c1, c2, c3, c4;
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};
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int hdmi5_read_edid(struct hdmi_core_data *core, u8 *edid, int len);
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void hdmi5_core_dump(struct hdmi_core_data *core, struct seq_file *s);
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int hdmi5_core_handle_irqs(struct hdmi_core_data *core);
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void hdmi5_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
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struct hdmi_config *cfg);
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int hdmi5_core_init(struct platform_device *pdev, struct hdmi_core_data *core);
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int hdmi5_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp,
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struct omap_dss_audio *audio, u32 pclk);
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#endif
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