/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _R819XU_PHYREG_H
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#define _R819XU_PHYREG_H
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#define RF_DATA 0x1d4 /* FW will write RF data in the register.*/
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/* page8 */
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#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
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#define rFPGA0_TxGainStage 0x80c
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#define rFPGA0_XA_HSSIParameter1 0x820
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#define rFPGA0_XA_HSSIParameter2 0x824
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#define rFPGA0_XB_HSSIParameter1 0x828
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#define rFPGA0_XB_HSSIParameter2 0x82c
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#define rFPGA0_XC_HSSIParameter1 0x830
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#define rFPGA0_XC_HSSIParameter2 0x834
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#define rFPGA0_XD_HSSIParameter1 0x838
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#define rFPGA0_XD_HSSIParameter2 0x83c
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#define rFPGA0_XA_LSSIParameter 0x840
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#define rFPGA0_XB_LSSIParameter 0x844
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#define rFPGA0_XC_LSSIParameter 0x848
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#define rFPGA0_XD_LSSIParameter 0x84c
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#define rFPGA0_XAB_SwitchControl 0x858
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#define rFPGA0_XCD_SwitchControl 0x85c
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#define rFPGA0_XA_RFInterfaceOE 0x860
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#define rFPGA0_XB_RFInterfaceOE 0x864
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#define rFPGA0_XC_RFInterfaceOE 0x868
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#define rFPGA0_XD_RFInterfaceOE 0x86c
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#define rFPGA0_XAB_RFInterfaceSW 0x870
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#define rFPGA0_XCD_RFInterfaceSW 0x874
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#define rFPGA0_XAB_RFParameter 0x878
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#define rFPGA0_XCD_RFParameter 0x87c
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#define rFPGA0_AnalogParameter1 0x880
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#define rFPGA0_AnalogParameter4 0x88c
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#define rFPGA0_XA_LSSIReadBack 0x8a0
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#define rFPGA0_XB_LSSIReadBack 0x8a4
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#define rFPGA0_XC_LSSIReadBack 0x8a8
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#define rFPGA0_XD_LSSIReadBack 0x8ac
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#define rFPGA0_XAB_RFInterfaceRB 0x8e0
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#define rFPGA0_XCD_RFInterfaceRB 0x8e4
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/* page 9 */
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#define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */
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/* page a */
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#define rCCK0_System 0xa00
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#define rCCK0_AFESetting 0xa04
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#define rCCK0_CCA 0xa08
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#define rCCK0_TxFilter1 0xa20
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#define rCCK0_TxFilter2 0xa24
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#define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
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/* page c */
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#define rOFDM0_TRxPathEnable 0xc04
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#define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
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#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */
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#define rOFDM0_XBRxAFE 0xc18
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#define rOFDM0_XBRxIQImbalance 0xc1c
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#define rOFDM0_XCRxAFE 0xc20
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#define rOFDM0_XCRxIQImbalance 0xc24
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#define rOFDM0_XDRxAFE 0xc28
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#define rOFDM0_XDRxIQImbalance 0xc2c
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#define rOFDM0_RxDetector1 0xc30 /* PD,BW & SBD */
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#define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync.*/
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#define rOFDM0_RxDetector3 0xc38 /* Frame Sync.*/
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#define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
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#define rOFDM0_XAAGCCore1 0xc50
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#define rOFDM0_XAAGCCore2 0xc54
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#define rOFDM0_XBAGCCore1 0xc58
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#define rOFDM0_XBAGCCore2 0xc5c
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#define rOFDM0_XCAGCCore1 0xc60
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#define rOFDM0_XCAGCCore2 0xc64
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#define rOFDM0_XDAGCCore1 0xc68
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#define rOFDM0_XDAGCCore2 0xc6c
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#define rOFDM0_XATxIQImbalance 0xc80
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#define rOFDM0_XATxAFE 0xc84
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#define rOFDM0_XBTxIQImbalance 0xc88
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#define rOFDM0_XBTxAFE 0xc8c
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#define rOFDM0_XCTxIQImbalance 0xc90
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#define rOFDM0_XCTxAFE 0xc94
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#define rOFDM0_XDTxIQImbalance 0xc98
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#define rOFDM0_XDTxAFE 0xc9c
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/* page d */
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#define rOFDM1_LSTF 0xd00
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#define rOFDM1_TRxPathEnable 0xd04
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/* page e */
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#define rTxAGC_Rate18_06 0xe00
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#define rTxAGC_Rate54_24 0xe04
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#define rTxAGC_CCK_Mcs32 0xe08
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#define rTxAGC_Mcs03_Mcs00 0xe10
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#define rTxAGC_Mcs07_Mcs04 0xe14
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#define rTxAGC_Mcs11_Mcs08 0xe18
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#define rTxAGC_Mcs15_Mcs12 0xe1c
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/* RF
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* Zebra1
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*/
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#define rZebra1_Channel 0x7
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/* Zebra4 */
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#define rGlobalCtrl 0
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/* Bit Mask
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* page-8
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*/
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#define bRFMOD 0x1
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#define bCCKEn 0x1000000
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#define bOFDMEn 0x2000000
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#define bXBTxAGC 0xf00
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#define bXCTxAGC 0xf000
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#define b3WireDataLength 0x800
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#define b3WireAddressLength 0x400
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#define bRFSI_RFENV 0x10
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#define bLSSIReadAddress 0x3f000000 /* LSSI "Read" Address */
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#define bLSSIReadEdge 0x80000000 /* LSSI "Read" edge signal */
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#define bLSSIReadBackData 0xfff
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#define bXtalCap 0x0f000000
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/* page-a */
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#define bCCKSideBand 0x10
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/* page e */
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#define bTxAGCRateCCK 0x7f00
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/* RF
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* Zebra1
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*/
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#define bZebra1_ChannelNum 0xf80
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/* RTL8258 */
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/* for PutRegsetting & GetRegSetting BitMask */
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#define bMaskByte0 0xff
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#define bMaskByte1 0xff00
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#define bMaskByte2 0xff0000
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#define bMaskHWord 0xffff0000
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#define bMaskLWord 0x0000ffff
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#define bMaskDWord 0xffffffff
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/* for PutRFRegsetting & GetRFRegSetting BitMask */
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#define bMask12Bits 0xfff
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#endif /* __INC_HAL8190PCIPHYREG_H */
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