/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* This is part of rtl8187 OpenSource driver.
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* Copyright (C) Andrea Merello 2004-2005 <andrea.merello@gmail.com>
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*
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* Parts of this driver are based on the GPL part of the
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* official Realtek driver.
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* Parts of this driver are based on the rtl8180 driver skeleton
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* from Patric Schenke & Andres Salomon.
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* Parts of this driver are based on the Intel Pro Wireless
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* 2100 GPL driver.
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*
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* We want to thank the Authors of those projects
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* and the Ndiswrapper project Authors.
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*/
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/* Mariusz Matuszek added full registers definition with Realtek's name */
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/* this file contains register definitions for the rtl8187 MAC controller */
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#ifndef R8192_HW
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#define R8192_HW
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#define RTL8187_REQT_READ 0xc0
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#define RTL8187_REQT_WRITE 0x40
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#define RTL8187_REQ_GET_REGS 0x05
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#define RTL8187_REQ_SET_REGS 0x05
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#define MAX_TX_URB 5
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#define MAX_RX_URB 16
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#define R8180_MAX_RETRY 255
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#define RX_URB_SIZE 9100
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#define RTL8190_EEPROM_ID 0x8129
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#define EEPROM_VID 0x02
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#define EEPROM_PID 0x04
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#define EEPROM_NODE_ADDRESS_BYTE_0 0x0C
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#define EEPROM_TX_POWER_DIFF 0x1F
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#define EEPROM_THERMAL_METER 0x20
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#define EEPROM_PW_DIFF 0x21 //0x21
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#define EEPROM_CRYSTAL_CAP 0x22 //0x22
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#define EEPROM_TX_PW_INDEX_CCK 0x23 //0x23
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#define EEPROM_TX_PW_INDEX_OFDM_24G 0x24 //0x24~0x26
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#define EEPROM_TX_PW_INDEX_CCK_V1 0x29 //0x29~0x2B
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#define EEPROM_TX_PW_INDEX_OFDM_24G_V1 0x2C //0x2C~0x2E
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#define EEPROM_TX_PW_INDEX_VER 0x27 //0x27
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#define EEPROM_DEFAULT_THERNAL_METER 0x7
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#define EEPROM_DEFAULT_PW_DIFF 0x4
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#define EEPROM_DEFAULT_CRYSTAL_CAP 0x5
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#define EEPROM_DEFAULT_TX_POWER 0x1010
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#define EEPROM_CUSTOMER_ID 0x7B //0x7B:CustomerID
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#define EEPROM_CHANNEL_PLAN 0x16 //0x7C
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#define EEPROM_CID_RUNTOP 0x2
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#define EEPROM_CID_DLINK 0x8
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#define AC_PARAM_TXOP_LIMIT_OFFSET 16
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#define AC_PARAM_ECW_MAX_OFFSET 12
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#define AC_PARAM_ECW_MIN_OFFSET 8
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#define AC_PARAM_AIFS_OFFSET 0
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//#endif
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enum _RTL8192Usb_HW {
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MAC0 = 0x000,
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MAC4 = 0x004,
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#define BB_GLOBAL_RESET_BIT 0x1
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BB_GLOBAL_RESET = 0x020, // BasebandGlobal Reset Register
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BSSIDR = 0x02E, // BSSID Register
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CMDR = 0x037, // Command register
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#define CR_RE 0x08
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#define CR_TE 0x04
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SIFS = 0x03E, // SIFS register
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#define TCR_MXDMA_2048 7
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#define TCR_LRL_OFFSET 0
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#define TCR_SRL_OFFSET 8
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#define TCR_MXDMA_OFFSET 21
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#define TCR_SAT BIT(24) // Enable Rate depedent ack timeout timer
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RCR = 0x044, // Receive Configuration Register
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#define MAC_FILTER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(5) | \
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BIT(12) | BIT(18) | BIT(19) | BIT(20) | BIT(21) | \
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BIT(22) | BIT(23))
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#define RX_FIFO_THRESHOLD_MASK (BIT(13) | BIT(14) | BIT(15))
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#define RX_FIFO_THRESHOLD_SHIFT 13
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#define RX_FIFO_THRESHOLD_NONE 7
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#define MAX_RX_DMA_MASK (BIT(8) | BIT(9) | BIT(10))
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#define RCR_MXDMA_OFFSET 8
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#define RCR_FIFO_OFFSET 13
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#define RCR_ONLYERLPKT BIT(31) // Early Receiving based on Packet Size.
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#define RCR_CBSSID BIT(23) // Accept BSSID match packet
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#define RCR_APWRMGT BIT(22) // Accept power management packet
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#define RCR_AMF BIT(20) // Accept management type frame
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#define RCR_ACF BIT(19) // Accept control type frame
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#define RCR_ADF BIT(18) // Accept data type frame
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#define RCR_AICV BIT(12) // Accept ICV error packet
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#define RCR_ACRC32 BIT(5) // Accept CRC32 error packet
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#define RCR_AB BIT(3) // Accept broadcast packet
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#define RCR_AM BIT(2) // Accept multicast packet
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#define RCR_APM BIT(1) // Accept physical match packet
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#define RCR_AAP BIT(0) // Accept all unicast packet
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SLOT_TIME = 0x049, // Slot Time Register
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ACK_TIMEOUT = 0x04c, // Ack Timeout Register
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EDCAPARA_BE = 0x050, // EDCA Parameter of AC BE
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EDCAPARA_BK = 0x054, // EDCA Parameter of AC BK
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EDCAPARA_VO = 0x058, // EDCA Parameter of AC VO
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EDCAPARA_VI = 0x05C, // EDCA Parameter of AC VI
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BCN_TCFG = 0x062, // Beacon Time Configuration
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#define BCN_TCFG_CW_SHIFT 8
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#define BCN_TCFG_IFS 0
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BCN_INTERVAL = 0x070, // Beacon Interval (TU)
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ATIMWND = 0x072, // ATIM Window Size (TU)
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BCN_DRV_EARLY_INT = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT
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BCN_DMATIME = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA
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BCN_ERR_THRESH = 0x078, // Beacon Error Threshold
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RWCAM = 0x0A0, //IN 8190 Data Sheet is called CAMcmd
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WCAMI = 0x0A4, // Software write CAM input content
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SECR = 0x0B0, //Security Configuration Register
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#define SCR_TxUseDK BIT(0) //Force Tx Use Default Key
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#define SCR_RxUseDK BIT(1) //Force Rx Use Default Key
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#define SCR_TxEncEnable BIT(2) //Enable Tx Encryption
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#define SCR_RxDecEnable BIT(3) //Enable Rx Decryption
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#define SCR_SKByA2 BIT(4) //Search kEY BY A2
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#define SCR_NoSKMC BIT(5) //No Key Search for Multicast
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//----------------------------------------------------------------------------
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// 8190 CPU General Register (offset 0x100, 4 byte)
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//----------------------------------------------------------------------------
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#define CPU_CCK_LOOPBACK 0x00030000
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#define CPU_GEN_SYSTEM_RESET 0x00000001
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#define CPU_GEN_FIRMWARE_RESET 0x00000008
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#define CPU_GEN_BOOT_RDY 0x00000010
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#define CPU_GEN_FIRM_RDY 0x00000020
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#define CPU_GEN_PUT_CODE_OK 0x00000080
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#define CPU_GEN_BB_RST 0x00000100
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#define CPU_GEN_PWR_STB_CPU 0x00000004
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#define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
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#define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
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CPU_GEN = 0x100, // CPU Reset Register
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AcmHwCtrl = 0x171, // ACM Hardware Control Register
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//----------------------------------------------------------------------------
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////
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//// 8190 AcmHwCtrl bits (offset 0x171, 1 byte)
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////----------------------------------------------------------------------------
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//
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#define AcmHw_BeqEn BIT(1)
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RQPN1 = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk
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RQPN2 = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High
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RQPN3 = 0x188, // Reserved Queue Page Number, Bcn, Public,
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QPNR = 0x1D0, //0x1F0, // Queue Packet Number report per TID
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#define BW_OPMODE_5G BIT(1)
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#define BW_OPMODE_20MHZ BIT(2)
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BW_OPMODE = 0x300, // Bandwidth operation mode
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MSR = 0x303, // Media Status register
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#define MSR_LINK_MASK (BIT(0)|BIT(1))
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#define MSR_LINK_MANAGED 2
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#define MSR_LINK_NONE 0
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#define MSR_LINK_SHIFT 0
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#define MSR_LINK_ADHOC 1
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#define MSR_LINK_MASTER 3
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RETRY_LIMIT = 0x304, // Retry Limit [15:8]-short, [7:0]-long
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#define RETRY_LIMIT_SHORT_SHIFT 8
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#define RETRY_LIMIT_LONG_SHIFT 0
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RRSR = 0x310, // Response Rate Set
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#define RRSR_1M BIT(0)
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#define RRSR_2M BIT(1)
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#define RRSR_5_5M BIT(2)
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#define RRSR_11M BIT(3)
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#define RRSR_6M BIT(4)
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#define RRSR_9M BIT(5)
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#define RRSR_12M BIT(6)
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#define RRSR_18M BIT(7)
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#define RRSR_24M BIT(8)
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#define RRSR_36M BIT(9)
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#define RRSR_48M BIT(10)
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#define RRSR_54M BIT(11)
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#define BRSR_AckShortPmb BIT(23) // CCK ACK: use Short Preamble or not.
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UFWP = 0x318,
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RATR0 = 0x320, // Rate Adaptive Table register1
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DRIVER_RSSI = 0x32c, // Driver tell Firmware current RSSI
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//----------------------------------------------------------------------------
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// 8190 Rate Adaptive Table Register (offset 0x320, 4 byte)
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//----------------------------------------------------------------------------
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//CCK
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#define RATR_1M 0x00000001
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#define RATR_2M 0x00000002
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#define RATR_55M 0x00000004
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#define RATR_11M 0x00000008
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//OFDM
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#define RATR_6M 0x00000010
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#define RATR_9M 0x00000020
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#define RATR_12M 0x00000040
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#define RATR_18M 0x00000080
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#define RATR_24M 0x00000100
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#define RATR_36M 0x00000200
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#define RATR_48M 0x00000400
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#define RATR_54M 0x00000800
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//MCS 1 Spatial Stream
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#define RATR_MCS0 0x00001000
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#define RATR_MCS1 0x00002000
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#define RATR_MCS2 0x00004000
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#define RATR_MCS3 0x00008000
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#define RATR_MCS4 0x00010000
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#define RATR_MCS5 0x00020000
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#define RATR_MCS6 0x00040000
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#define RATR_MCS7 0x00080000
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//MCS 2 Spatial Stream
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#define RATR_MCS8 0x00100000
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#define RATR_MCS9 0x00200000
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#define RATR_MCS10 0x00400000
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#define RATR_MCS11 0x00800000
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#define RATR_MCS12 0x01000000
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#define RATR_MCS13 0x02000000
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#define RATR_MCS14 0x04000000
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#define RATR_MCS15 0x08000000
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// ALL CCK Rate
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#define RATE_ALL_CCK RATR_1M|RATR_2M|RATR_55M|RATR_11M
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#define RATE_ALL_OFDM_AG RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M\
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|RATR_36M|RATR_48M|RATR_54M
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#define RATE_ALL_OFDM_1SS RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \
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RATR_MCS4|RATR_MCS5|RATR_MCS6|RATR_MCS7
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#define RATE_ALL_OFDM_2SS RATR_MCS8|RATR_MCS9 |RATR_MCS10|RATR_MCS11| \
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RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
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EPROM_CMD = 0xfe58,
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#define Cmd9346CR_9356SEL BIT(4)
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#define EPROM_CMD_OPERATING_MODE_SHIFT 6
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#define EPROM_CMD_NORMAL 0
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#define EPROM_CMD_PROGRAM 2
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#define EPROM_CS_BIT BIT(3)
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#define EPROM_CK_BIT BIT(2)
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#define EPROM_W_BIT BIT(1)
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#define EPROM_R_BIT BIT(0)
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};
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//----------------------------------------------------------------------------
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// 818xB AnaParm & AnaParm2 Register
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//----------------------------------------------------------------------------
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#define GPI 0x108
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#endif
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