/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#ifndef __RTL8188E_XMIT_H__
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#define __RTL8188E_XMIT_H__
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#define MAX_TX_AGG_PACKET_NUMBER 0xFF
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/* */
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/* Queue Select Value in TxDesc */
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/* */
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#define QSLT_BK 0x2/* 0x01 */
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#define QSLT_BE 0x0
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#define QSLT_VI 0x5/* 0x4 */
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#define QSLT_VO 0x7/* 0x6 */
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#define QSLT_BEACON 0x10
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#define QSLT_HIGH 0x11
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#define QSLT_MGNT 0x12
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#define QSLT_CMD 0x13
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/* For 88e early mode */
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#define SET_EARLYMODE_PKTNUM(__pAddr, __Value) \
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SET_BITS_TO_LE_4BYTE(__pAddr, 0, 3, __Value)
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#define SET_EARLYMODE_LEN0(__pAddr, __Value) \
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SET_BITS_TO_LE_4BYTE(__pAddr, 4, 12, __Value)
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#define SET_EARLYMODE_LEN1(__pAddr, __Value) \
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SET_BITS_TO_LE_4BYTE(__pAddr, 16, 12, __Value)
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#define SET_EARLYMODE_LEN2_1(__pAddr, __Value) \
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SET_BITS_TO_LE_4BYTE(__pAddr, 28, 4, __Value)
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#define SET_EARLYMODE_LEN2_2(__pAddr, __Value) \
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SET_BITS_TO_LE_4BYTE(__pAddr + 4, 0, 8, __Value)
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#define SET_EARLYMODE_LEN3(__pAddr, __Value) \
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SET_BITS_TO_LE_4BYTE(__pAddr + 4, 8, 12, __Value)
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#define SET_EARLYMODE_LEN4(__pAddr, __Value) \
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SET_BITS_TO_LE_4BYTE(__pAddr + 4, 20, 12, __Value)
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/* */
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/* defined for TX DESC Operation */
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/* */
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#define MAX_TID (15)
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/* OFFSET 0 */
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#define OFFSET_SZ 0
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#define OFFSET_SHT 16
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#define BMC BIT(24)
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#define LSG BIT(26)
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#define FSG BIT(27)
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#define OWN BIT(31)
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/* OFFSET 4 */
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#define PKT_OFFSET_SZ 0
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#define QSEL_SHT 8
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#define RATE_ID_SHT 16
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#define NAVUSEHDR BIT(20)
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#define SEC_TYPE_SHT 22
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#define PKT_OFFSET_SHT 26
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/* OFFSET 8 */
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#define AGG_EN BIT(12)
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#define AGG_BK BIT(16)
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#define AMPDU_DENSITY_SHT 20
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#define ANTSEL_A BIT(24)
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#define ANTSEL_B BIT(25)
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#define TX_ANT_CCK_SHT 26
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#define TX_ANTL_SHT 28
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#define TX_ANT_HT_SHT 30
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/* OFFSET 12 */
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#define SEQ_SHT 16
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#define EN_HWSEQ BIT(31)
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/* OFFSET 16 */
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#define QOS BIT(6)
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#define HW_SSN BIT(7)
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#define USERATE BIT(8)
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#define DISDATAFB BIT(10)
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#define CTS_2_SELF BIT(11)
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#define RTS_EN BIT(12)
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#define HW_RTS_EN BIT(13)
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#define DATA_SHORT BIT(24)
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#define PWR_STATUS_SHT 15
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#define DATA_SC_SHT 20
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#define DATA_BW BIT(25)
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/* OFFSET 20 */
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#define RTY_LMT_EN BIT(17)
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enum TXDESC_SC {
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SC_DONT_CARE = 0x00,
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SC_UPPER = 0x01,
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SC_LOWER = 0x02,
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SC_DUPLICATE = 0x03
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};
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/* OFFSET 20 */
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#define SGI BIT(6)
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#define USB_TXAGG_NUM_SHT 24
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#define txdesc_set_ccx_sw_88e(txdesc, value) \
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do { \
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((struct txdesc_88e *)(txdesc))->sw1 = (((value) >> 8) & 0x0f); \
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((struct txdesc_88e *)(txdesc))->sw0 = ((value) & 0xff); \
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} while (0)
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struct txrpt_ccx_88e {
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/* offset 0 */
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u8 tag1:1;
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u8 pkt_num:3;
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u8 txdma_underflow:1;
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u8 int_bt:1;
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u8 int_tri:1;
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u8 int_ccx:1;
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/* offset 1 */
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u8 mac_id:6;
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u8 pkt_ok:1;
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u8 bmc:1;
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/* offset 2 */
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u8 retry_cnt:6;
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u8 lifetime_over:1;
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u8 retry_over:1;
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/* offset 3 */
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u8 ccx_qtime0;
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u8 ccx_qtime1;
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/* offset 5 */
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u8 final_data_rate;
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/* offset 6 */
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u8 sw1:4;
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u8 qsel:4;
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/* offset 7 */
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u8 sw0;
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};
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#define txrpt_ccx_sw_88e(txrpt_ccx) ((txrpt_ccx)->sw0 + ((txrpt_ccx)->sw1 << 8))
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#define txrpt_ccx_qtime_88e(txrpt_ccx) \
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((txrpt_ccx)->ccx_qtime0 + ((txrpt_ccx)->ccx_qtime1 << 8))
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void rtl8188e_fill_fake_txdesc(struct adapter *padapter, u8 *pDesc,
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u32 BufferLen, u8 IsPsPoll, u8 IsBTQosNull);
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s32 rtl8188eu_init_xmit_priv(struct adapter *padapter);
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s32 rtl8188eu_xmit_buf_handler(struct adapter *padapter);
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#define hal_xmit_handler rtl8188eu_xmit_buf_handler
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void rtl8188eu_xmit_tasklet(struct tasklet_struct *t);
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bool rtl8188eu_xmitframe_complete(struct adapter *padapter,
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struct xmit_priv *pxmitpriv);
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void handle_txrpt_ccx_88e(struct adapter *adapter, u8 *buf);
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void _dbg_dump_tx_info(struct adapter *padapter, int frame_tag,
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struct tx_desc *ptxdesc);
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#endif /* __RTL8188E_XMIT_H__ */
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