/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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*******************************************************************************/
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#ifndef __RTL8188E_SPEC_H__
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#define __RTL8188E_SPEC_H__
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/* 8192C Register offset definition */
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#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */
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#define HAL_92C_NAV_UPPER_UNIT 128 /* micro-second */
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#define MAC_ADDR_LEN 6
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/* 8188E PKT_BUFF_ACCESS_CTRL value */
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#define TXPKT_BUF_SELECT 0x69
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#define RXPKT_BUF_SELECT 0xA5
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#define DISABLE_TRXPKT_BUF_ACCESS 0x0
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/* 0x0000h ~ 0x00FFh System Configuration */
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#define REG_SYS_ISO_CTRL 0x0000
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#define REG_SYS_FUNC_EN 0x0002
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#define REG_APS_FSMCO 0x0004
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#define REG_SYS_CLKR 0x0008
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#define REG_9346CR 0x000A
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#define REG_EE_VPD 0x000C
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#define REG_AFE_MISC 0x0010
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#define REG_SPS0_CTRL 0x0011
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#define REG_SPS_OCP_CFG 0x0018
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#define REG_RSV_CTRL 0x001C
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#define REG_RF_CTRL 0x001F
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#define REG_LDOA15_CTRL 0x0020
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#define REG_LDOV12D_CTRL 0x0021
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#define REG_LDOHCI12_CTRL 0x0022
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#define REG_LPLDO_CTRL 0x0023
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#define REG_AFE_XTAL_CTRL 0x0024
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#define REG_AFE_PLL_CTRL 0x0028
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#define REG_APE_PLL_CTRL_EXT 0x002c
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#define REG_EFUSE_CTRL 0x0030
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#define REG_EFUSE_TEST 0x0034
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#define REG_GPIO_MUXCFG 0x0040
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#define REG_GPIO_IO_SEL 0x0042
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#define REG_MAC_PINMUX_CFG 0x0043
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#define REG_GPIO_PIN_CTRL 0x0044
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#define REG_GPIO_INTM 0x0048
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#define REG_LEDCFG0 0x004C
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#define REG_LEDCFG1 0x004D
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#define REG_LEDCFG2 0x004E
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#define REG_LEDCFG3 0x004F
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#define REG_FSIMR 0x0050
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#define REG_FSISR 0x0054
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#define REG_HSIMR 0x0058
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#define REG_HSISR 0x005c
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#define REG_GPIO_PIN_CTRL_2 0x0060 /* RTL8723 WIFI/BT/GPS
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* Multi-Function GPIO Pin Control.
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*/
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#define REG_GPIO_IO_SEL_2 0x0062 /* RTL8723 WIFI/BT/GPS
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* Multi-Function GPIO Select.
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*/
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#define REG_BB_PAD_CTRL 0x0064
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#define REG_MULTI_FUNC_CTRL 0x0068 /* RTL8723 WIFI/BT/GPS
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* Multi-Function control source.
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*/
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#define REG_GPIO_OUTPUT 0x006c
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#define REG_AFE_XTAL_CTRL_EXT 0x0078 /* RTL8188E */
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#define REG_XCK_OUT_CTRL 0x007c /* RTL8188E */
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#define REG_MCUFWDL 0x0080
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#define REG_WOL_EVENT 0x0081 /* RTL8188E */
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#define REG_MCUTSTCFG 0x0084
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#define REG_HMEBOX_E0 0x0088
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#define REG_HMEBOX_E1 0x008A
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#define REG_HMEBOX_E2 0x008C
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#define REG_HMEBOX_E3 0x008E
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#define REG_HMEBOX_EXT_0 0x01F0
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#define REG_HMEBOX_EXT_1 0x01F4
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#define REG_HMEBOX_EXT_2 0x01F8
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#define REG_HMEBOX_EXT_3 0x01FC
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#define REG_HIMR_88E 0x00B0
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#define REG_HISR_88E 0x00B4
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#define REG_HIMRE_88E 0x00B8
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#define REG_HISRE_88E 0x00BC
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#define REG_EFUSE_ACCESS 0x00CF /* Efuse access protection
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* for RTL8723
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*/
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#define REG_BIST_SCAN 0x00D0
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#define REG_BIST_RPT 0x00D4
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#define REG_BIST_ROM_RPT 0x00D8
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#define REG_USB_SIE_INTF 0x00E0
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#define REG_PCIE_MIO_INTF 0x00E4
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#define REG_PCIE_MIO_INTD 0x00E8
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#define REG_HPON_FSM 0x00EC
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#define REG_SYS_CFG 0x00F0
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#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only. */
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#define REG_TYPE_ID 0x00FC
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#define REG_MAC_PHY_CTRL_NORMAL 0x00f8
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/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
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#define REG_CR 0x0100
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#define REG_PBP 0x0104
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#define REG_PKT_BUFF_ACCESS_CTRL 0x0106
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#define REG_TRXDMA_CTRL 0x010C
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#define REG_TRXFF_BNDY 0x0114
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#define REG_TRXFF_STATUS 0x0118
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#define REG_RXFF_PTR 0x011C
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/* define REG_HIMR 0x0120 */
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/* define REG_HISR 0x0124 */
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#define REG_HIMRE 0x0128
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#define REG_HISRE 0x012C
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#define REG_CPWM 0x012F
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#define REG_FWIMR 0x0130
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#define REG_FTIMR 0x0138
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#define REG_FWISR 0x0134
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#define REG_PKTBUF_DBG_CTRL 0x0140
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#define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
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#define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL + 2)
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#define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL + 3)
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#define REG_RXPKTBUF_CTRL (REG_PKTBUF_DBG_CTRL + 2)
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#define REG_PKTBUF_DBG_DATA_L 0x0144
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#define REG_PKTBUF_DBG_DATA_H 0x0148
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#define REG_TC0_CTRL 0x0150
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#define REG_TC1_CTRL 0x0154
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#define REG_TC2_CTRL 0x0158
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#define REG_TC3_CTRL 0x015C
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#define REG_TC4_CTRL 0x0160
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#define REG_TCUNIT_BASE 0x0164
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#define REG_MBIST_START 0x0174
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#define REG_MBIST_DONE 0x0178
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#define REG_MBIST_FAIL 0x017C
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#define REG_32K_CTRL 0x0194 /* RTL8188E */
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#define REG_C2HEVT_MSG_NORMAL 0x01A0
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#define REG_C2HEVT_CLEAR 0x01AF
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#define REG_MCUTST_1 0x01c0
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#define REG_FMETHR 0x01C8
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#define REG_HMETFR 0x01CC
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#define REG_HMEBOX_0 0x01D0
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#define REG_HMEBOX_1 0x01D4
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#define REG_HMEBOX_2 0x01D8
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#define REG_HMEBOX_3 0x01DC
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#define REG_LLT_INIT 0x01E0
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/* 0x0200h ~ 0x027Fh TXDMA Configuration */
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#define REG_RQPN 0x0200
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#define REG_FIFOPAGE 0x0204
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#define REG_TDECTRL 0x0208
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#define REG_TXDMA_OFFSET_CHK 0x020C
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#define REG_TXDMA_STATUS 0x0210
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#define REG_RQPN_NPQ 0x0214
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/* 0x0280h ~ 0x02FFh RXDMA Configuration */
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#define REG_RXDMA_AGG_PG_TH 0x0280
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#define REG_RXPKT_NUM 0x0284
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#define REG_RXDMA_STATUS 0x0288
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/* 0x0300h ~ 0x03FFh PCIe */
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#define REG_PCIE_CTRL_REG 0x0300
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#define REG_INT_MIG 0x0304 /* Interrupt Migration */
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#define REG_BCNQ_DESA 0x0308 /* TX Beacon Descr Address */
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#define REG_HQ_DESA 0x0310 /* TX High Queue Descr Addr */
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#define REG_MGQ_DESA 0x0318 /* TX Manage Queue Descr Addr*/
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#define REG_VOQ_DESA 0x0320 /* TX VO Queue Descr Addr */
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#define REG_VIQ_DESA 0x0328 /* TX VI Queue Descr Addr */
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#define REG_BEQ_DESA 0x0330 /* TX BE Queue Descr Addr */
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#define REG_BKQ_DESA 0x0338 /* TX BK Queue Descr Addr */
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#define REG_RX_DESA 0x0340 /* RX Queue Descr Addr */
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#define REG_MDIO 0x0354 /* MDIO for Access PCIE PHY */
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#define REG_DBG_SEL 0x0360 /* Debug Selection Register */
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#define REG_PCIE_HRPWM 0x0361 /* PCIe RPWM */
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#define REG_PCIE_HCPWM 0x0363 /* PCIe CPWM */
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#define REG_WATCH_DOG 0x0368
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/* RTL8723 series ------------------------------ */
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#define REG_PCIE_HISR 0x03A0
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/* spec version 11 */
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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#define REG_VOQ_INFORMATION 0x0400
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#define REG_VIQ_INFORMATION 0x0404
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#define REG_BEQ_INFORMATION 0x0408
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#define REG_BKQ_INFORMATION 0x040C
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#define REG_MGQ_INFORMATION 0x0410
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#define REG_HGQ_INFORMATION 0x0414
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#define REG_BCNQ_INFORMATION 0x0418
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#define REG_TXPKT_EMPTY 0x041A
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#define REG_CPU_MGQ_INFORMATION 0x041C
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#define REG_FWHW_TXQ_CTRL 0x0420
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#define REG_HWSEQ_CTRL 0x0423
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#define REG_TXPKTBUF_BCNQ_BDNY 0x0424
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#define REG_TXPKTBUF_MGQ_BDNY 0x0425
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#define REG_LIFETIME_EN 0x0426
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#define REG_MULTI_BCNQ_OFFSET 0x0427
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#define REG_SPEC_SIFS 0x0428
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#define REG_RL 0x042A
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#define REG_DARFRC 0x0430
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#define REG_RARFRC 0x0438
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#define REG_RRSR 0x0440
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#define REG_ARFR0 0x0444
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#define REG_ARFR1 0x0448
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#define REG_ARFR2 0x044C
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#define REG_ARFR3 0x0450
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#define REG_AGGLEN_LMT 0x0458
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#define REG_AMPDU_MIN_SPACE 0x045C
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#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D
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#define REG_FAST_EDCA_CTRL 0x0460
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#define REG_RD_RESP_PKT_TH 0x0463
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#define REG_INIRTS_RATE_SEL 0x0480
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/* define REG_INIDATA_RATE_SEL 0x0484 */
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#define REG_POWER_STATUS 0x04A4
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#define REG_POWER_STAGE1 0x04B4
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#define REG_POWER_STAGE2 0x04B8
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#define REG_PKT_VO_VI_LIFE_TIME 0x04C0
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#define REG_PKT_BE_BK_LIFE_TIME 0x04C2
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#define REG_STBC_SETTING 0x04C4
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#define REG_PROT_MODE_CTRL 0x04C8
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#define REG_MAX_AGGR_NUM 0x04CA
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#define REG_RTS_MAX_AGGR_NUM 0x04CB
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#define REG_BAR_MODE_CTRL 0x04CC
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#define REG_RA_TRY_RATE_AGG_LMT 0x04CF
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#define REG_EARLY_MODE_CONTROL 0x4D0
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#define REG_NQOS_SEQ 0x04DC
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#define REG_QOS_SEQ 0x04DE
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#define REG_NEED_CPU_HANDLE 0x04E0
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#define REG_PKT_LOSE_RPT 0x04E1
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#define REG_PTCL_ERR_STATUS 0x04E2
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#define REG_TX_RPT_CTRL 0x04EC
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#define REG_TX_RPT_TIME 0x04F0 /* 2 byte */
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#define REG_DUMMY 0x04FC
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/* 0x0500h ~ 0x05FFh EDCA Configuration */
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#define REG_EDCA_VO_PARAM 0x0500
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#define REG_EDCA_VI_PARAM 0x0504
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#define REG_EDCA_BE_PARAM 0x0508
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#define REG_EDCA_BK_PARAM 0x050C
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#define REG_BCNTCFG 0x0510
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#define REG_PIFS 0x0512
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#define REG_RDG_PIFS 0x0513
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#define REG_SIFS_CTX 0x0514
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#define REG_SIFS_TRX 0x0516
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#define REG_TSFTR_SYN_OFFSET 0x0518
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#define REG_AGGR_BREAK_TIME 0x051A
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#define REG_SLOT 0x051B
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#define REG_TX_PTCL_CTRL 0x0520
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#define REG_TXPAUSE 0x0522
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#define REG_DIS_TXREQ_CLR 0x0523
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#define REG_RD_CTRL 0x0524
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/* Format for offset 540h-542h:
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* [3:0]: TBTT prohibit setup in unit of 32us. The time for HW getting
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* beacon content before TBTT.
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*
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* [7:4]: Reserved.
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* [19:8]: TBTT prohibit hold in unit of 32us. The time for HW holding
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* to send the beacon packet.
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*
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* [23:20]: Reserved
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* Description:
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* |
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* |<--Setup--|--Hold------------>|
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* --------------|----------------------
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* |
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* TBTT
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* Note: We cannot update beacon content to HW or send any AC packets during
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* the time between Setup and Hold.
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*/
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#define REG_TBTT_PROHIBIT 0x0540
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#define REG_RD_NAV_NXT 0x0544
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#define REG_NAV_PROT_LEN 0x0546
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#define REG_BCN_CTRL 0x0550
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#define REG_BCN_CTRL_1 0x0551
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#define REG_MBID_NUM 0x0552
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#define REG_DUAL_TSF_RST 0x0553
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#define REG_BCN_INTERVAL 0x0554
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#define REG_DRVERLYINT 0x0558
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#define REG_BCNDMATIM 0x0559
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#define REG_ATIMWND 0x055A
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#define REG_BCN_MAX_ERR 0x055D
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#define REG_RXTSF_OFFSET_CCK 0x055E
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#define REG_RXTSF_OFFSET_OFDM 0x055F
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#define REG_TSFTR 0x0560
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#define REG_TSFTR1 0x0568
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#define REG_ATIMWND_1 0x0570
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#define REG_PSTIMER 0x0580
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#define REG_TIMER0 0x0584
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#define REG_TIMER1 0x0588
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#define REG_ACMHWCTRL 0x05C0
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/* define REG_FW_TSF_SYNC_CNT 0x04A0 */
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#define REG_FW_RESET_TSF_CNT_1 0x05FC
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#define REG_FW_RESET_TSF_CNT_0 0x05FD
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#define REG_FW_BCN_DIS_CNT 0x05FE
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/* 0x0600h ~ 0x07FFh WMAC Configuration */
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#define REG_APSD_CTRL 0x0600
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#define REG_BWOPMODE 0x0603
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#define REG_TCR 0x0604
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#define REG_RCR 0x0608
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#define REG_RX_PKT_LIMIT 0x060C
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#define REG_RX_DLK_TIME 0x060D
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#define REG_RX_DRVINFO_SZ 0x060F
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#define REG_MACID 0x0610
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#define REG_BSSID 0x0618
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#define REG_MAR 0x0620
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#define REG_MBIDCAMCFG 0x0628
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#define REG_USTIME_EDCA 0x0638
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#define REG_MAC_SPEC_SIFS 0x063A
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/* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
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/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
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#define REG_R2T_SIFS 0x063C
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/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
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#define REG_T2T_SIFS 0x063E
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#define REG_ACKTO 0x0640
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#define REG_CTS2TO 0x0641
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#define REG_EIFS 0x0642
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/* RXERR_RPT */
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#define RXERR_TYPE_OFDM_PPDU 0
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#define RXERR_TYPE_OFDM_false_ALARM 1
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#define RXERR_TYPE_OFDM_MPDU_OK 2
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#define RXERR_TYPE_OFDM_MPDU_FAIL 3
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#define RXERR_TYPE_CCK_PPDU 4
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#define RXERR_TYPE_CCK_false_ALARM 5
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#define RXERR_TYPE_CCK_MPDU_OK 6
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#define RXERR_TYPE_CCK_MPDU_FAIL 7
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#define RXERR_TYPE_HT_PPDU 8
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#define RXERR_TYPE_HT_false_ALARM 9
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#define RXERR_TYPE_HT_MPDU_TOTAL 10
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#define RXERR_TYPE_HT_MPDU_OK 11
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#define RXERR_TYPE_HT_MPDU_FAIL 12
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#define RXERR_TYPE_RX_FULL_DROP 15
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#define RXERR_COUNTER_MASK 0xFFFFF
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#define RXERR_RPT_RST BIT(27)
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#define _RXERR_RPT_SEL(type) ((type) << 28)
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/* Note:
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* The NAV upper value is very important to WiFi 11n 5.2.3 NAV test.
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* The default value is always too small, but the WiFi TestPlan test
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* by 25,000 microseconds of NAV through sending CTS in the air.
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* We must update this value greater than 25,000 microseconds to pass
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* the item. The offset of NAV_UPPER in 8192C Spec is incorrect, and
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* the offset should be 0x0652.
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*/
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#define REG_NAV_UPPER 0x0652 /* unit of 128 */
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/* WMA, BA, CCX */
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/* define REG_NAV_CTRL 0x0650 */
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#define REG_BACAMCMD 0x0654
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#define REG_BACAMCONTENT 0x0658
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#define REG_LBDLY 0x0660
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#define REG_FWDLY 0x0661
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#define REG_RXERR_RPT 0x0664
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#define REG_WMAC_TRXPTCL_CTL 0x0668
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/* Security */
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#define REG_CAMCMD 0x0670
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#define REG_CAMWRITE 0x0674
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#define REG_CAMREAD 0x0678
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#define REG_CAMDBG 0x067C
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#define REG_SECCFG 0x0680
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/* Power */
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#define REG_WOW_CTRL 0x0690
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#define REG_PS_RX_INFO 0x0692
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#define REG_UAPSD_TID 0x0693
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#define REG_WKFMCAM_CMD 0x0698
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#define REG_WKFMCAM_NUM_88E 0x698
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#define REG_RXFLTMAP0 0x06A0
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#define REG_RXFLTMAP1 0x06A2
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#define REG_RXFLTMAP2 0x06A4
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#define REG_BCN_PSR_RPT 0x06A8
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#define REG_BT_COEX_TABLE 0x06C0
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/* Hardware Port 2 */
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#define REG_MACID1 0x0700
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#define REG_BSSID1 0x0708
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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#define REG_USB_INFO 0xFE17
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#define REG_USB_SPECIAL_OPTION 0xFE55
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#define REG_USB_DMA_AGG_TO 0xFE5B
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#define REG_USB_AGG_TO 0xFE5C
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#define REG_USB_AGG_TH 0xFE5D
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/* For normal chip */
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#define REG_NORMAL_SIE_VID 0xFE60 /* 0xFE60~0xFE61 */
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#define REG_NORMAL_SIE_PID 0xFE62 /* 0xFE62~0xFE63 */
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#define REG_NORMAL_SIE_OPTIONAL 0xFE64
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#define REG_NORMAL_SIE_EP 0xFE65 /* 0xFE65~0xFE67 */
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#define REG_NORMAL_SIE_PHY 0xFE68 /* 0xFE68~0xFE6B */
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#define REG_NORMAL_SIE_OPTIONAL2 0xFE6C
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#define REG_NORMAL_SIE_GPS_EP 0xFE6D /* 0xFE6D, for RTL8723 only. */
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#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 /* 0xFE70~0xFE75 */
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#define REG_NORMAL_SIE_STRING 0xFE80 /* 0xFE80~0xFEDF */
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/* TODO: use these definition when using REG_xxx naming rule. */
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/* NOTE: DO NOT Remove these definition. Use later. */
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#define EFUSE_CTRL REG_EFUSE_CTRL /* E-Fuse Control. */
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#define EFUSE_TEST REG_EFUSE_TEST /* E-Fuse Test. */
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#define MSR (REG_CR + 2) /* Media Status reg */
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#define ISR REG_HISR_88E
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/* Timing Sync Function Timer Register. */
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#define TSFR REG_TSFTR
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#define PBP REG_PBP
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/* Redifine MACID register, to compatible prior ICs. */
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/* MAC ID Register, Offset 0x0050-0x0053 */
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#define IDR0 REG_MACID
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/* MAC ID Register, Offset 0x0054-0x0055 */
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#define IDR4 (REG_MACID + 4)
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/* 9. Security Control Registers (Offset: ) */
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/* IN 8190 Data Sheet is called CAMcmd */
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#define RWCAM REG_CAMCMD
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/* Software write CAM input content */
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#define WCAMI REG_CAMWRITE
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/* Software read/write CAM config */
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#define RCAMO REG_CAMREAD
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#define CAMDBG REG_CAMDBG
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/* Security Configuration Register */
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#define SECR REG_SECCFG
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/* Unused register */
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#define UnusedRegister 0x1BF
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#define DCAM UnusedRegister
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#define PSR UnusedRegister
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#define BBAddr UnusedRegister
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#define PhyDataR UnusedRegister
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/* Min Spacing related settings. */
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#define MAX_MSS_DENSITY_2T 0x13
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#define MAX_MSS_DENSITY_1T 0x0A
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/* EEPROM enable when set 1 */
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#define CmdEEPROM_En BIT(5)
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/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
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#define CmdEERPOMSEL BIT(4)
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#define Cmd9346CR_9356SEL BIT(4)
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/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */
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#define GPIOSEL_GPIO 0
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#define GPIOSEL_ENBT BIT(5)
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/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */
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/* GPIO pins input value */
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#define GPIO_IN REG_GPIO_PIN_CTRL
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/* GPIO pins output value */
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#define GPIO_OUT (REG_GPIO_PIN_CTRL + 1)
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/* GPIO pins output enable when a bit is set to "1"; otherwise,
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* input is configured.
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*/
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#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL + 2)
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#define GPIO_MOD (REG_GPIO_PIN_CTRL + 3)
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/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
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#define HSIMR_GPIO12_0_INT_EN BIT(0)
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#define HSIMR_SPS_OCP_INT_EN BIT(5)
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#define HSIMR_RON_INT_EN BIT(6)
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#define HSIMR_PDN_INT_EN BIT(7)
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#define HSIMR_GPIO9_INT_EN BIT(25)
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/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
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#define HSISR_GPIO12_0_INT BIT(0)
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#define HSISR_SPS_OCP_INT BIT(5)
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#define HSISR_RON_INT_EN BIT(6)
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#define HSISR_PDNINT BIT(7)
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#define HSISR_GPIO9_INT BIT(25)
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/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */
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/*
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* Network Type
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* 00: No link
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* 01: Link in ad hoc network
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* 10: Link in infrastructure network
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* 11: AP mode
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* Default: 00b.
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*/
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#define MSR_NOLINK 0x00
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#define MSR_ADHOC 0x01
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#define MSR_INFRA 0x02
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#define MSR_AP 0x03
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/* 88EU (MSR) Media Status Register (Offset 0x4C, 8 bits) */
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#define USB_INTR_CONTENT_C2H_OFFSET 0
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#define USB_INTR_CONTENT_CPWM1_OFFSET 16
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#define USB_INTR_CONTENT_CPWM2_OFFSET 20
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#define USB_INTR_CONTENT_HISR_OFFSET 48
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#define USB_INTR_CONTENT_HISRE_OFFSET 52
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/* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */
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/* IOL config for REG_FDHM0(Reg0x88) */
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#define CMD_INIT_LLT BIT(0)
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#define CMD_READ_EFUSE_MAP BIT(1)
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#define CMD_EFUSE_PATCH BIT(2)
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#define CMD_IOCONFIG BIT(3)
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#define CMD_INIT_LLT_ERR BIT(4)
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#define CMD_READ_EFUSE_MAP_ERR BIT(5)
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#define CMD_EFUSE_PATCH_ERR BIT(6)
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#define CMD_IOCONFIG_ERR BIT(7)
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/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
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/* 8192C Response Rate Set Register (offset 0x181, 24bits) */
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#define RRSR_1M BIT(0)
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#define RRSR_2M BIT(1)
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#define RRSR_5_5M BIT(2)
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#define RRSR_11M BIT(3)
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#define RRSR_6M BIT(4)
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#define RRSR_9M BIT(5)
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#define RRSR_12M BIT(6)
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#define RRSR_18M BIT(7)
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#define RRSR_24M BIT(8)
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#define RRSR_36M BIT(9)
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#define RRSR_48M BIT(10)
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#define RRSR_54M BIT(11)
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#define RRSR_MCS0 BIT(12)
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#define RRSR_MCS1 BIT(13)
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#define RRSR_MCS2 BIT(14)
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#define RRSR_MCS3 BIT(15)
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#define RRSR_MCS4 BIT(16)
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#define RRSR_MCS5 BIT(17)
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#define RRSR_MCS6 BIT(18)
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#define RRSR_MCS7 BIT(19)
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/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */
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/* WOL bit information */
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#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
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#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
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/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
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#define BW_OPMODE_20MHZ BIT(2)
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#define BW_OPMODE_5G BIT(1)
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/* 8192C CAM Config Setting (offset 0x250, 1 byte) */
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#define CAM_VALID BIT(15)
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#define CAM_NOTVALID 0x0000
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#define CAM_USEDK BIT(5)
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#define CAM_CONTENT_COUNT 8
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#define CAM_NONE 0x0
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#define CAM_WEP40 0x01
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#define CAM_TKIP 0x02
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#define CAM_AES 0x04
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#define CAM_WEP104 0x05
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#define CAM_SMS4 0x6
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#define TOTAL_CAM_ENTRY 32
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#define HALF_CAM_ENTRY 16
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#define CAM_CONFIG_USEDK true
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#define CAM_CONFIG_NO_USEDK false
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#define CAM_WRITE BIT(16)
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#define CAM_READ 0x00000000
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#define CAM_POLLINIG BIT(31)
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#define SCR_UseDK 0x01
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#define SCR_TxSecEnable 0x02
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#define SCR_RxSecEnable 0x04
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/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
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#define WOW_PMEN BIT(0) /* Power management Enable. */
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#define WOW_WOMEN BIT(1) /* WoW function on or off. */
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#define WOW_MAGIC BIT(2) /* Magic packet */
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#define WOW_UWF BIT(3) /* Unicast Wakeup frame. */
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/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
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/* 8188 IMR/ISR bits */
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#define IMR_DISABLED_88E 0x0
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/* IMR DW0(0x0060-0063) Bit 0-31 */
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#define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */
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#define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */
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#define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
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#define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
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#define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */
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#define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */
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#define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
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#define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */
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#define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */
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#define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
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#define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
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#define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */
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#define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
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#define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
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#define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
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#define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
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#define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */
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#define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */
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#define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */
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#define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */
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#define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */
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#define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */
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#define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */
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#define IMR_ROK_88E BIT(0) /* Receive DMA OK */
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/* IMR DW1(0x00B4-00B7) Bit 0-31 */
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#define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */
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#define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */
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#define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */
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#define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */
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#define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */
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#define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */
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#define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */
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#define IMR_BCNDERR7_88E BIT(20) /* Beacon DMA Error Int 7 */
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#define IMR_BCNDERR6_88E BIT(19) /* Beacon DMA Error Int 6 */
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#define IMR_BCNDERR5_88E BIT(18) /* Beacon DMA Error Int 5 */
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#define IMR_BCNDERR4_88E BIT(17) /* Beacon DMA Error Int 4 */
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#define IMR_BCNDERR3_88E BIT(16) /* Beacon DMA Error Int 3 */
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#define IMR_BCNDERR2_88E BIT(15) /* Beacon DMA Error Int 2 */
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#define IMR_BCNDERR1_88E BIT(14) /* Beacon DMA Error Int 1 */
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#define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Ext for Win7 */
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#define IMR_TXERR_88E BIT(11) /* Tx Err Flag Int Status, write 1 clear. */
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#define IMR_RXERR_88E BIT(10) /* Rx Err Flag INT Status, Write 1 clear */
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#define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */
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#define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */
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#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */
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/* 8192C EFUSE */
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#define HWSET_MAX_SIZE 256
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#define HWSET_MAX_SIZE_88E 512
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/*===================================================================
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=====================================================================
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Here the register defines are for 92C. When the define is as same with 92C,
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we will use the 92C's define for the consistency
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So the following defines for 92C is not entire!!!!!!
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=====================================================================
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=====================================================================*/
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/*
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* Based on Datasheet V33---090401
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* Register Summary
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* Current IOREG MAP
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* 0x0000h ~ 0x00FFh System Configuration (256 Bytes)
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* 0x0100h ~ 0x01FFh MACTOP General Configuration (256 Bytes)
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* 0x0200h ~ 0x027Fh TXDMA Configuration (128 Bytes)
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* 0x0280h ~ 0x02FFh RXDMA Configuration (128 Bytes)
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* 0x0300h ~ 0x03FFh PCIE EMAC Reserved Region (256 Bytes)
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* 0x0400h ~ 0x04FFh Protocol Configuration (256 Bytes)
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* 0x0500h ~ 0x05FFh EDCA Configuration (256 Bytes)
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* 0x0600h ~ 0x07FFh WMAC Configuration (512 Bytes)
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* 0x2000h ~ 0x3FFFh 8051 FW Download Region (8196 Bytes)
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*/
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/* 8192C (TXPAUSE) transmission pause (Offset 0x522, 8 bits) */
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/* Note:
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* The bits of stopping AC(VO/VI/BE/BK) queue in datasheet
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* RTL8192S/RTL8192C are wrong,
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* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2,
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* and BK - Bit3.
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* 8723 and 88E may be not correct either in the earlier version.
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*/
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#define StopBecon BIT(6)
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#define StopHigh BIT(5)
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#define StopMgt BIT(4)
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#define StopBK BIT(3)
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#define StopBE BIT(2)
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#define StopVI BIT(1)
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#define StopVO BIT(0)
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/* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */
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#define RCR_APPFCS BIT(31) /* WMAC append FCS after payload */
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#define RCR_APP_MIC BIT(30)
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#define RCR_APP_PHYSTS BIT(28)
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#define RCR_APP_ICV BIT(29)
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#define RCR_APP_PHYST_RXFF BIT(28)
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#define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */
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#define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */
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#define RCR_LSIGEN BIT(23)
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#define RCR_MFBEN BIT(22)
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#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
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#define RCR_AMF BIT(13) /* Accept management type frame */
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#define RCR_ACF BIT(12) /* Accept control type frame */
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#define RCR_ADF BIT(11) /* Accept data type frame */
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#define RCR_AICV BIT(9) /* Accept ICV error packet */
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#define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */
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#define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet
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* (Rx beacon, probe rsp)
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*/
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#define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match (Data)*/
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#define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */
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#define RCR_APWRMGT BIT(5) /* Accept power management pkt*/
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#define RCR_ADD3 BIT(4) /* Accept address 3 match pkt */
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#define RCR_AB BIT(3) /* Accept broadcast packet */
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#define RCR_AM BIT(2) /* Accept multicast packet */
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#define RCR_APM BIT(1) /* Accept physical match pkt */
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#define RCR_AAP BIT(0) /* Accept all unicast packet */
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#define RCR_MXDMA_OFFSET 8
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#define RCR_FIFO_OFFSET 13
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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#define REG_USB_INFO 0xFE17
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#define REG_USB_SPECIAL_OPTION 0xFE55
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#define REG_USB_DMA_AGG_TO 0xFE5B
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#define REG_USB_AGG_TO 0xFE5C
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#define REG_USB_AGG_TH 0xFE5D
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#define REG_USB_HRPWM 0xFE58
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#define REG_USB_HCPWM 0xFE57
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/* 8192C Register Bit and Content definition */
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/* 0x0000h ~ 0x00FFh System Configuration */
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/* 2 SYS_ISO_CTRL */
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#define ISO_MD2PP BIT(0)
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#define ISO_UA2USB BIT(1)
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#define ISO_UD2CORE BIT(2)
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#define ISO_PA2PCIE BIT(3)
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#define ISO_PD2CORE BIT(4)
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#define ISO_IP2MAC BIT(5)
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#define ISO_DIOP BIT(6)
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#define ISO_DIOE BIT(7)
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#define ISO_EB2CORE BIT(8)
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#define ISO_DIOR BIT(9)
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#define PWC_EV12V BIT(15)
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/* 2 SYS_FUNC_EN */
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#define FEN_BBRSTB BIT(0)
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#define FEN_BB_GLB_RSTn BIT(1)
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#define FEN_USBA BIT(2)
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#define FEN_UPLL BIT(3)
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#define FEN_USBD BIT(4)
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#define FEN_DIO_PCIE BIT(5)
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#define FEN_PCIEA BIT(6)
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#define FEN_PPLL BIT(7)
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#define FEN_PCIED BIT(8)
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#define FEN_DIOE BIT(9)
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#define FEN_CPUEN BIT(10)
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#define FEN_DCORE BIT(11)
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#define FEN_ELDR BIT(12)
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#define FEN_DIO_RF BIT(13)
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#define FEN_HWPDN BIT(14)
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#define FEN_MREGEN BIT(15)
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/* 2 APS_FSMCO */
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#define PFM_LDALL BIT(0)
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#define PFM_ALDN BIT(1)
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#define PFM_LDKP BIT(2)
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#define PFM_WOWL BIT(3)
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#define EnPDN BIT(4)
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#define PDN_PL BIT(5)
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#define APFM_ONMAC BIT(8)
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#define APFM_OFF BIT(9)
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#define APFM_RSM BIT(10)
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#define AFSM_HSUS BIT(11)
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#define AFSM_PCIE BIT(12)
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#define APDM_MAC BIT(13)
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#define APDM_HOST BIT(14)
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#define APDM_HPDN BIT(15)
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#define RDY_MACON BIT(16)
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#define SUS_HOST BIT(17)
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#define ROP_ALD BIT(20)
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#define ROP_PWR BIT(21)
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#define ROP_SPS BIT(22)
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#define SOP_MRST BIT(25)
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#define SOP_FUSE BIT(26)
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#define SOP_ABG BIT(27)
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#define SOP_AMB BIT(28)
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#define SOP_RCK BIT(29)
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#define SOP_A8M BIT(30)
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#define XOP_BTCK BIT(31)
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/* 2 SYS_CLKR */
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#define ANAD16V_EN BIT(0)
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#define ANA8M BIT(1)
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#define MACSLP BIT(4)
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#define LOADER_CLK_EN BIT(5)
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/* 2 9346CR */
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#define BOOT_FROM_EEPROM BIT(4)
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#define EEPROM_EN BIT(5)
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/* 2 SPS0_CTRL */
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/* 2 SPS_OCP_CFG */
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/* 2 RF_CTRL */
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#define RF_EN BIT(0)
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#define RF_RSTB BIT(1)
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#define RF_SDMRSTB BIT(2)
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/* 2 LDOV12D_CTRL */
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#define LDV12_EN BIT(0)
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#define LDV12_SDBY BIT(1)
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#define LPLDO_HSM BIT(2)
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#define LPLDO_LSM_DIS BIT(3)
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#define _LDV12_VADJ(x) (((x) & 0xF) << 4)
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/* 2EFUSE_CTRL */
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#define ALD_EN BIT(18)
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#define EF_PD BIT(19)
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#define EF_FLAG BIT(31)
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/* 2 EFUSE_TEST (For RTL8723 partially) */
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#define EF_TRPT BIT(7)
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/* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
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#define EF_CELL_SEL (BIT(8) | BIT(9))
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#define LDOE25_EN BIT(31)
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#define EFUSE_SEL(x) (((x) & 0x3) << 8)
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#define EFUSE_SEL_MASK 0x300
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#define EFUSE_WIFI_SEL_0 0x0
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#define EFUSE_BT_SEL_0 0x1
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#define EFUSE_BT_SEL_1 0x2
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#define EFUSE_BT_SEL_2 0x3
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#define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */
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#define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */
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/* 2 8051FWDL */
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/* 2 MCUFWDL */
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#define MCUFWDL_EN BIT(0)
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#define MCUFWDL_RDY BIT(1)
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#define FWDL_CHKSUM_RPT BIT(2)
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#define MACINI_RDY BIT(3)
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#define BBINI_RDY BIT(4)
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#define RFINI_RDY BIT(5)
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#define WINTINI_RDY BIT(6)
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#define RAM_DL_SEL BIT(7) /* 1:RAM, 0:ROM */
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#define ROM_DLEN BIT(19)
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#define CPRST BIT(23)
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/* 2 REG_SYS_CFG */
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#define XCLK_VLD BIT(0)
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#define ACLK_VLD BIT(1)
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#define UCLK_VLD BIT(2)
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#define PCLK_VLD BIT(3)
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#define PCIRSTB BIT(4)
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#define V15_VLD BIT(5)
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#define SW_OFFLOAD_EN BIT(7)
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#define SIC_IDLE BIT(8)
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#define BD_MAC2 BIT(9)
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#define BD_MAC1 BIT(10)
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#define IC_MACPHY_MODE BIT(11)
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#define CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
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#define BT_FUNC BIT(16)
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#define VENDOR_ID BIT(19)
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#define PAD_HWPD_IDN BIT(22)
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#define TRP_VAUX_EN BIT(23) /* RTL ID */
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#define TRP_BT_EN BIT(24)
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#define BD_PKG_SEL BIT(25)
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#define BD_HCI_SEL BIT(26)
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#define TYPE_ID BIT(27)
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#define CHIP_VER_RTL_MASK 0xF000 /* Bit 12 ~ 15 */
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#define CHIP_VER_RTL_SHIFT 12
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/* 2REG_GPIO_OUTSTS (For RTL8723 only) */
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#define EFS_HCI_SEL (BIT(0) | BIT(1))
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#define PAD_HCI_SEL (BIT(2) | BIT(3))
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#define HCI_SEL (BIT(4) | BIT(5))
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#define PKG_SEL_HCI BIT(6)
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#define FEN_GPS BIT(7)
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#define FEN_BT BIT(8)
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#define FEN_WL BIT(9)
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#define FEN_PCI BIT(10)
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#define FEN_USB BIT(11)
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#define BTRF_HWPDN_N BIT(12)
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#define WLRF_HWPDN_N BIT(13)
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#define PDN_BT_N BIT(14)
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#define PDN_GPS_N BIT(15)
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#define BT_CTL_HWPDN BIT(16)
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#define GPS_CTL_HWPDN BIT(17)
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#define PPHY_SUSB BIT(20)
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#define UPHY_SUSB BIT(21)
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#define PCI_SUSEN BIT(22)
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#define USB_SUSEN BIT(23)
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#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
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/* 2SYS_CFG */
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#define RTL_ID BIT(23) /* TestChip ID, 1:Test(RLE); 0:MP(RL) */
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/* 0x0100h ~ 0x01FFh MACTOP General Configuration */
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/* 2 Function Enable Registers */
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/* 2 CR */
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#define HCI_TXDMA_EN BIT(0)
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#define HCI_RXDMA_EN BIT(1)
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#define TXDMA_EN BIT(2)
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#define RXDMA_EN BIT(3)
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#define PROTOCOL_EN BIT(4)
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#define SCHEDULE_EN BIT(5)
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#define MACTXEN BIT(6)
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#define MACRXEN BIT(7)
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#define ENSWBCN BIT(8)
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#define ENSEC BIT(9)
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#define CALTMR_EN BIT(10) /* 32k CAL TMR enable */
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/* Network type */
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#define _NETTYPE(x) (((x) & 0x3) << 16)
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#define MASK_NETTYPE 0x30000
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#define NT_NO_LINK 0x0
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#define NT_LINK_AD_HOC 0x1
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#define NT_LINK_AP 0x2
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#define NT_AS_AP 0x3
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/* 2 PBP - Page Size Register */
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#define GET_RX_PAGE_SIZE(value) ((value) & 0xF)
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#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4)
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#define _PSRX_MASK 0xF
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#define _PSTX_MASK 0xF0
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#define _PSRX(x) (x)
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#define _PSTX(x) ((x) << 4)
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#define PBP_64 0x0
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#define PBP_128 0x1
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#define PBP_256 0x2
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#define PBP_512 0x3
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#define PBP_1024 0x4
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/* 2 TX/RXDMA */
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#define RXDMA_ARBBW_EN BIT(0)
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#define RXSHFT_EN BIT(1)
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#define RXDMA_AGG_EN BIT(2)
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#define QS_VO_QUEUE BIT(8)
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#define QS_VI_QUEUE BIT(9)
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#define QS_BE_QUEUE BIT(10)
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#define QS_BK_QUEUE BIT(11)
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#define QS_MANAGER_QUEUE BIT(12)
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#define QS_HIGH_QUEUE BIT(13)
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#define HQSEL_VOQ BIT(0)
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#define HQSEL_VIQ BIT(1)
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#define HQSEL_BEQ BIT(2)
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#define HQSEL_BKQ BIT(3)
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#define HQSEL_MGTQ BIT(4)
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#define HQSEL_HIQ BIT(5)
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/* For normal driver, 0x10C */
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#define _TXDMA_HIQ_MAP(x) (((x) & 0x3) << 14)
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#define _TXDMA_MGQ_MAP(x) (((x) & 0x3) << 12)
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#define _TXDMA_BKQ_MAP(x) (((x) & 0x3) << 10)
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#define _TXDMA_BEQ_MAP(x) (((x) & 0x3) << 8)
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#define _TXDMA_VIQ_MAP(x) (((x) & 0x3) << 6)
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#define _TXDMA_VOQ_MAP(x) (((x) & 0x3) << 4)
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#define QUEUE_LOW 1
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#define QUEUE_NORMAL 2
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#define QUEUE_HIGH 3
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/* 2 TRXFF_BNDY */
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/* 2 LLT_INIT */
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#define _LLT_NO_ACTIVE 0x0
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#define _LLT_WRITE_ACCESS 0x1
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#define _LLT_READ_ACCESS 0x2
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#define _LLT_INIT_DATA(x) ((x) & 0xFF)
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#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8)
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#define _LLT_OP(x) (((x) & 0x3) << 30)
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#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3)
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/* 0x0200h ~ 0x027Fh TXDMA Configuration */
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/* 2RQPN */
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#define _HPQ(x) ((x) & 0xFF)
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#define _LPQ(x) (((x) & 0xFF) << 8)
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#define _PUBQ(x) (((x) & 0xFF) << 16)
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/* NOTE: in RQPN_NPQ register */
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#define _NPQ(x) ((x) & 0xFF)
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#define HPQ_PUBLIC_DIS BIT(24)
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#define LPQ_PUBLIC_DIS BIT(25)
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#define LD_RQPN BIT(31)
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/* 2TDECTRL */
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#define BCN_VALID BIT(16)
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#define BCN_HEAD(x) (((x) & 0xFF) << 8)
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#define BCN_HEAD_MASK 0xFF00
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/* 2 TDECTL */
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#define BLK_DESC_NUM_SHIFT 4
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#define BLK_DESC_NUM_MASK 0xF
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/* 2 TXDMA_OFFSET_CHK */
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#define DROP_DATA_EN BIT(9)
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/* 0x0280h ~ 0x028Bh RX DMA Configuration */
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/* REG_RXDMA_CONTROL, 0x0286h */
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/* 2 REG_RXPKT_NUM, 0x0284 */
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#define RXPKT_RELEASE_POLL BIT(16)
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#define RXDMA_IDLE BIT(17)
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#define RW_RELEASE_EN BIT(18)
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/* 0x0400h ~ 0x047Fh Protocol Configuration */
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/* 2 FWHW_TXQ_CTRL */
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#define EN_AMPDU_RTY_NEW BIT(7)
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/* 2 SPEC SIFS */
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#define _SPEC_SIFS_CCK(x) ((x) & 0xFF)
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#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8)
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/* 2 RL */
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#define RETRY_LIMIT_SHORT_SHIFT 8
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#define RETRY_LIMIT_LONG_SHIFT 0
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/* 0x0500h ~ 0x05FFh EDCA Configuration */
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/* 2 EDCA setting */
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#define AC_PARAM_TXOP_LIMIT_OFFSET 16
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#define AC_PARAM_ECW_MAX_OFFSET 12
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#define AC_PARAM_ECW_MIN_OFFSET 8
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#define AC_PARAM_AIFS_OFFSET 0
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#define _LRL(x) ((x) & 0x3F)
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#define _SRL(x) (((x) & 0x3F) << 8)
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/* 2 BCN_CTRL */
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#define EN_MBSSID BIT(1)
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#define EN_TXBCN_RPT BIT(2)
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#define EN_BCN_FUNCTION BIT(3)
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#define DIS_TSF_UPDATE BIT(3)
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/* The same function but different bit field. */
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#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4)
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#define DIS_TSF_UDT0_TEST_CHIP BIT(5)
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#define STOP_BCNQ BIT(6)
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/* 2 ACMHWCTRL */
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#define AcmHw_HwEn BIT(0)
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#define AcmHw_BeqEn BIT(1)
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#define AcmHw_ViqEn BIT(2)
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#define AcmHw_VoqEn BIT(3)
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#define AcmHw_BeqStatus BIT(4)
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#define AcmHw_ViqStatus BIT(5)
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#define AcmHw_VoqStatus BIT(6)
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/* 0x0600h ~ 0x07FFh WMAC Configuration */
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/* 2APSD_CTRL */
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#define APSDOFF BIT(6)
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#define APSDOFF_STATUS BIT(7)
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#define RATE_BITMAP_ALL 0xFFFFF
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/* Only use CCK 1M rate for ACK */
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#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1
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/* 2 TCR */
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#define TSFRST BIT(0)
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#define DIS_GCLK BIT(1)
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#define PAD_SEL BIT(2)
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#define PWR_ST BIT(6)
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#define PWRBIT_OW_EN BIT(7)
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#define ACRC BIT(8)
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#define CFENDFORM BIT(9)
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#define ICV BIT(10)
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/* 2 RCR */
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#define AAP BIT(0)
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#define APM BIT(1)
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#define AM BIT(2)
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#define AB BIT(3)
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#define ADD3 BIT(4)
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#define APWRMGT BIT(5)
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#define CBSSID BIT(6)
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#define CBSSID_DATA BIT(6)
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#define CBSSID_BCN BIT(7)
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#define ACRC32 BIT(8)
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#define AICV BIT(9)
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#define ADF BIT(11)
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#define ACF BIT(12)
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#define AMF BIT(13)
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#define HTC_LOC_CTRL BIT(14)
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#define UC_DATA_EN BIT(16)
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#define BM_DATA_EN BIT(17)
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#define MFBEN BIT(22)
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#define LSIGEN BIT(23)
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#define EnMBID BIT(24)
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#define APP_BASSN BIT(27)
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#define APP_PHYSTS BIT(28)
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#define APP_ICV BIT(29)
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#define APP_MIC BIT(30)
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#define APP_FCS BIT(31)
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/* 2 SECCFG */
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#define SCR_TxUseDK BIT(0) /* Force Tx Use Default Key */
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#define SCR_RxUseDK BIT(1) /* Force Rx Use Default Key */
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#define SCR_TxEncEnable BIT(2) /* Enable Tx Encryption */
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#define SCR_RxDecEnable BIT(3) /* Enable Rx Decryption */
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#define SCR_SKByA2 BIT(4) /* Search kEY BY A2 */
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#define SCR_NoSKMC BIT(5) /* No Key Search Multicast */
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#define SCR_TXBCUSEDK BIT(6) /* Force Tx Bcast pkt Use Default Key */
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#define SCR_RXBCUSEDK BIT(7) /* Force Rx Bcast pkt Use Default Key */
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/* RTL8188E SDIO Configuration */
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/* I/O bus domain address mapping */
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#define SDIO_LOCAL_BASE 0x10250000
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#define WLAN_IOREG_BASE 0x10260000
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#define FIRMWARE_FIFO_BASE 0x10270000
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#define TX_HIQ_BASE 0x10310000
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#define TX_MIQ_BASE 0x10320000
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#define TX_LOQ_BASE 0x10330000
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#define RX_RX0FF_BASE 0x10340000
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/* SDIO host local register space mapping. */
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#define SDIO_LOCAL_MSK 0x0FFF
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#define WLAN_IOREG_MSK 0x7FFF
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#define WLAN_FIFO_MSK 0x1FFF /* Aggregation Length[12:0] */
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#define WLAN_RX0FF_MSK 0x0003
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/* Without ref to the SDIO Device ID */
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#define SDIO_WITHOUT_REF_DEVICE_ID 0
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#define SDIO_LOCAL_DEVICE_ID 0 /* 0b[16], 000b[15:13] */
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#define WLAN_TX_HIQ_DEVICE_ID 4 /* 0b[16], 100b[15:13] */
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#define WLAN_TX_MIQ_DEVICE_ID 5 /* 0b[16], 101b[15:13] */
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#define WLAN_TX_LOQ_DEVICE_ID 6 /* 0b[16], 110b[15:13] */
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#define WLAN_RX0FF_DEVICE_ID 7 /* 0b[16], 111b[15:13] */
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#define WLAN_IOREG_DEVICE_ID 8 /* 1b[16] */
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/* SDIO Tx Free Page Index */
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#define HI_QUEUE_IDX 0
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#define MID_QUEUE_IDX 1
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#define LOW_QUEUE_IDX 2
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#define PUBLIC_QUEUE_IDX 3
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#define SDIO_MAX_TX_QUEUE 3 /* HIQ, MIQ and LOQ */
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#define SDIO_MAX_RX_QUEUE 1
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/* SDIO Tx Control */
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#define SDIO_REG_TX_CTRL 0x0000
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/* SDIO Host Interrupt Mask */
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#define SDIO_REG_HIMR 0x0014
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/* SDIO Host Interrupt Service Routine */
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#define SDIO_REG_HISR 0x0018
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/* HCI Current Power Mode */
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#define SDIO_REG_HCPWM 0x0019
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/* RXDMA Request Length */
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#define SDIO_REG_RX0_REQ_LEN 0x001C
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/* Free Tx Buffer Page */
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#define SDIO_REG_FREE_TXPG 0x0020
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/* HCI Current Power Mode 1 */
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#define SDIO_REG_HCPWM1 0x0024
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/* HCI Current Power Mode 2 */
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#define SDIO_REG_HCPWM2 0x0026
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/* HTSF Informaion */
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#define SDIO_REG_HTSFR_INFO 0x0030
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/* HCI Request Power Mode 1 */
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#define SDIO_REG_HRPWM1 0x0080
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/* HCI Request Power Mode 2 */
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#define SDIO_REG_HRPWM2 0x0082
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/* HCI Power Save Clock */
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#define SDIO_REG_HPS_CLKR 0x0084
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/* SDIO HCI Suspend Control */
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#define SDIO_REG_HSUS_CTRL 0x0086
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/* SDIO Host Extension Interrupt Mask Always */
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#define SDIO_REG_HIMR_ON 0x0090
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/* SDIO Host Extension Interrupt Status Always */
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#define SDIO_REG_HISR_ON 0x0091
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#define SDIO_HIMR_DISABLED 0
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/* RTL8188E SDIO Host Interrupt Mask Register */
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#define SDIO_HIMR_RX_REQUEST_MSK BIT(0)
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#define SDIO_HIMR_AVAL_MSK BIT(1)
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#define SDIO_HIMR_TXERR_MSK BIT(2)
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#define SDIO_HIMR_RXERR_MSK BIT(3)
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#define SDIO_HIMR_TXFOVW_MSK BIT(4)
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#define SDIO_HIMR_RXFOVW_MSK BIT(5)
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#define SDIO_HIMR_TXBCNOK_MSK BIT(6)
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#define SDIO_HIMR_TXBCNERR_MSK BIT(7)
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#define SDIO_HIMR_BCNERLY_INT_MSK BIT(16)
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#define SDIO_HIMR_C2HCMD_MSK BIT(17)
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#define SDIO_HIMR_CPWM1_MSK BIT(18)
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#define SDIO_HIMR_CPWM2_MSK BIT(19)
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#define SDIO_HIMR_HSISR_IND_MSK BIT(20)
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#define SDIO_HIMR_GTINT3_IND_MSK BIT(21)
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#define SDIO_HIMR_GTINT4_IND_MSK BIT(22)
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#define SDIO_HIMR_PSTIMEOUT_MSK BIT(23)
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#define SDIO_HIMR_OCPINT_MSK BIT(24)
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#define SDIO_HIMR_ATIMEND_MSK BIT(25)
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#define SDIO_HIMR_ATIMEND_E_MSK BIT(26)
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#define SDIO_HIMR_CTWEND_MSK BIT(27)
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/* RTL8188E SDIO Specific */
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#define SDIO_HIMR_MCU_ERR_MSK BIT(28)
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#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT(29)
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/* SDIO Host Interrupt Service Routine */
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#define SDIO_HISR_RX_REQUEST BIT(0)
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#define SDIO_HISR_AVAL BIT(1)
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#define SDIO_HISR_TXERR BIT(2)
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#define SDIO_HISR_RXERR BIT(3)
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#define SDIO_HISR_TXFOVW BIT(4)
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#define SDIO_HISR_RXFOVW BIT(5)
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#define SDIO_HISR_TXBCNOK BIT(6)
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#define SDIO_HISR_TXBCNERR BIT(7)
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#define SDIO_HISR_BCNERLY_INT BIT(16)
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#define SDIO_HISR_C2HCMD BIT(17)
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#define SDIO_HISR_CPWM1 BIT(18)
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#define SDIO_HISR_CPWM2 BIT(19)
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#define SDIO_HISR_HSISR_IND BIT(20)
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#define SDIO_HISR_GTINT3_IND BIT(21)
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#define SDIO_HISR_GTINT4_IND BIT(22)
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#define SDIO_HISR_PSTIME BIT(23)
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#define SDIO_HISR_OCPINT BIT(24)
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#define SDIO_HISR_ATIMEND BIT(25)
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#define SDIO_HISR_ATIMEND_E BIT(26)
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#define SDIO_HISR_CTWEND BIT(27)
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/* RTL8188E SDIO Specific */
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#define SDIO_HISR_MCU_ERR BIT(28)
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#define SDIO_HISR_TSF_BIT32_TOGGLE BIT(29)
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#define MASK_SDIO_HISR_CLEAR \
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(SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\
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SDIO_HISR_RXFOVW | SDIO_HISR_TXBCNOK | SDIO_HISR_TXBCNERR |\
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SDIO_HISR_C2HCMD | SDIO_HISR_CPWM1 | SDIO_HISR_CPWM2 |\
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SDIO_HISR_HSISR_IND | SDIO_HISR_GTINT3_IND | SDIO_HISR_GTINT4_IND |\
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SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT)
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/* SDIO HCI Suspend Control Register */
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#define HCI_RESUME_PWR_RDY BIT(1)
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#define HCI_SUS_CTRL BIT(0)
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/* SDIO Tx FIFO related */
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/* The number of Tx FIFO free page */
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#define SDIO_TX_FREE_PG_QUEUE 4
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#define SDIO_TX_FIFO_PAGE_SZ 128
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/* 0xFE00h ~ 0xFE55h USB Configuration */
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/* 2 USB Information (0xFE17) */
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#define USB_IS_HIGH_SPEED 0
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#define USB_IS_FULL_SPEED 1
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#define USB_SPEED_MASK BIT(5)
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#define USB_NORMAL_SIE_EP_MASK 0xF
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#define USB_NORMAL_SIE_EP_SHIFT 4
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/* 2 Special Option */
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#define USB_AGG_EN BIT(3)
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/* 0; Use interrupt endpoint to upload interrupt pkt */
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/* 1; Use bulk endpoint to upload interrupt pkt, */
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#define INT_BULK_SEL BIT(4)
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/* 2REG_C2HEVT_CLEAR */
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/* Set by driver and notify FW that the driver has read
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* the C2H command message
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*/
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#define C2H_EVT_HOST_CLOSE 0x00
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/* Set by FW indicating that FW had set the C2H command
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* message and it's not yet read by driver.
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*/
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#define C2H_EVT_FW_CLOSE 0xFF
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/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
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/* Enable GPIO[9] as WiFi HW PDn source */
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#define WL_HWPDN_EN BIT(0)
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/* WiFi HW PDn polarity control */
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#define WL_HWPDN_SL BIT(1)
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/* WiFi function enable */
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#define WL_FUNC_EN BIT(2)
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/* Enable GPIO[9] as WiFi RF HW PDn source */
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#define WL_HWROF_EN BIT(3)
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/* Enable GPIO[11] as BT HW PDn source */
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#define BT_HWPDN_EN BIT(16)
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/* BT HW PDn polarity control */
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#define BT_HWPDN_SL BIT(17)
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/* BT function enable */
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#define BT_FUNC_EN BIT(18)
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/* Enable GPIO[11] as BT/GPS RF HW PDn source */
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#define BT_HWROF_EN BIT(19)
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/* Enable GPIO[10] as GPS HW PDn source */
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#define GPS_HWPDN_EN BIT(20)
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/* GPS HW PDn polarity control */
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#define GPS_HWPDN_SL BIT(21)
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/* GPS function enable */
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#define GPS_FUNC_EN BIT(22)
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/* 3 REG_LIFECTRL_CTRL */
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#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3)
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#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2)
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#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1)
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#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0)
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#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */
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/* General definitions */
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#define LAST_ENTRY_OF_TX_PKT_BUFFER 176 /* 22k 22528 bytes */
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#define POLLING_LLT_THRESHOLD 20
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#define POLLING_READY_TIMEOUT_COUNT 1000
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/* GPIO BIT */
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#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
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/* 8192C EEPROM/EFUSE share register definition. */
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/* EEPROM/Efuse PG Offset for 88EE/88EU/88ES */
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#define EEPROM_TX_PWR_INX_88E 0x10
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#define EEPROM_ChannelPlan_88E 0xB8
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#define EEPROM_XTAL_88E 0xB9
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#define EEPROM_THERMAL_METER_88E 0xBA
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#define EEPROM_IQK_LCK_88E 0xBB
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#define EEPROM_RF_BOARD_OPTION_88E 0xC1
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#define EEPROM_RF_FEATURE_OPTION_88E 0xC2
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#define EEPROM_RF_BT_SETTING_88E 0xC3
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#define EEPROM_VERSION_88E 0xC4
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#define EEPROM_CUSTOMERID_88E 0xC5
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#define EEPROM_RF_ANTENNA_OPT_88E 0xC9
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/* RTL88EE */
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#define EEPROM_MAC_ADDR_88EE 0xD0
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#define EEPROM_VID_88EE 0xD6
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#define EEPROM_DID_88EE 0xD8
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#define EEPROM_SVID_88EE 0xDA
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#define EEPROM_SMID_88EE 0xDC
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/* RTL88EU */
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#define EEPROM_MAC_ADDR_88EU 0xD7
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#define EEPROM_VID_88EU 0xD0
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#define EEPROM_PID_88EU 0xD2
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#define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4
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/* RTL88ES */
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#define EEPROM_MAC_ADDR_88ES 0x11A
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/* EEPROM/Efuse Value Type */
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#define EETYPE_TX_PWR 0x0
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/* Default Value for EEPROM or EFUSE!!! */
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#define EEPROM_Default_TSSI 0x0
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#define EEPROM_Default_TxPowerDiff 0x0
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#define EEPROM_Default_CrystalCap 0x5
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/* Default: 2X2, RTL8192CE(QFPN68) */
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#define EEPROM_Default_BoardType 0x02
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#define EEPROM_Default_TxPower 0x1010
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#define EEPROM_Default_HT2T_TxPwr 0x10
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#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
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#define EEPROM_Default_ThermalMeter 0x12
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#define EEPROM_Default_AntTxPowerDiff 0x0
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#define EEPROM_Default_TxPwDiff_CrystalCap 0x5
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#define EEPROM_Default_TxPowerLevel 0x2A
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#define EEPROM_Default_HT40_2SDiff 0x0
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/* HT20<->40 default Tx Power Index Difference */
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#define EEPROM_Default_HT20_Diff 2
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#define EEPROM_Default_LegacyHTTxPowerDiff 0x3
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#define EEPROM_Default_HT40_PwrMaxOffset 0
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#define EEPROM_Default_HT20_PwrMaxOffset 0
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#define EEPROM_Default_CrystalCap_88E 0x20
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#define EEPROM_Default_ThermalMeter_88E 0x18
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/* New EFUSE default value */
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#define EEPROM_DEFAULT_24G_INDEX 0x2D
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#define EEPROM_DEFAULT_24G_HT20_DIFF 0X02
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#define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04
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#define EEPROM_DEFAULT_5G_INDEX 0X2A
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#define EEPROM_DEFAULT_5G_HT20_DIFF 0X00
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#define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04
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#define EEPROM_DEFAULT_DIFF 0XFE
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#define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F
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#define EEPROM_DEFAULT_BOARD_OPTION 0x00
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#define EEPROM_DEFAULT_FEATURE_OPTION 0x00
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#define EEPROM_DEFAULT_BT_OPTION 0x10
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/* For debug */
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#define EEPROM_Default_PID 0x1234
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#define EEPROM_Default_VID 0x5678
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#define EEPROM_Default_CustomerID 0xAB
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#define EEPROM_Default_CustomerID_8188E 0x00
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#define EEPROM_Default_SubCustomerID 0xCD
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#define EEPROM_Default_Version 0
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#define EEPROM_CHANNEL_PLAN_FCC 0x0
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#define EEPROM_CHANNEL_PLAN_IC 0x1
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#define EEPROM_CHANNEL_PLAN_ETSI 0x2
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#define EEPROM_CHANNEL_PLAN_SPA 0x3
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#define EEPROM_CHANNEL_PLAN_FRANCE 0x4
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#define EEPROM_CHANNEL_PLAN_MKK 0x5
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#define EEPROM_CHANNEL_PLAN_MKK1 0x6
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#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
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#define EEPROM_CHANNEL_PLAN_TELEC 0x8
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#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMA 0x9
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#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
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#define EEPROM_CHANNEL_PLAN_NCC 0xB
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#define EEPROM_USB_OPTIONAL1 0xE
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#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
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#define EEPROM_CID_DEFAULT 0x0
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#define EEPROM_CID_TOSHIBA 0x4
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#define EEPROM_CID_CCX 0x10 /* CCX test. */
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#define EEPROM_CID_QMI 0x0D
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#define EEPROM_CID_WHQL 0xFE
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#define RTL_EEPROM_ID 0x8129
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#endif /* __RTL8188E_SPEC_H__ */
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