/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#ifndef __RTL8188E_HAL_H__
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#define __RTL8188E_HAL_H__
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/* include HAL Related header after HAL Related compiling flags */
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#include "rtl8188e_spec.h"
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#include "hal8188e_phy_reg.h"
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#include "hal8188e_phy_cfg.h"
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#include "rtl8188e_dm.h"
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#include "rtl8188e_recv.h"
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#include "rtl8188e_xmit.h"
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#include "rtl8188e_cmd.h"
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#include "pwrseq.h"
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#include "rtw_efuse.h"
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#include "rtw_sreset.h"
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#include "odm_precomp.h"
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/* Fw Array */
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#define Rtl8188E_FwImageArray Rtl8188EFwImgArray
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#define Rtl8188E_FWImgArrayLength Rtl8188EFWImgArrayLength
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#define RTL8188E_FW_UMC_IMG "rtl8188E\\rtl8188efw.bin"
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#define RTL8188E_PHY_REG "rtl8188E\\PHY_REG_1T.txt"
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#define RTL8188E_PHY_RADIO_A "rtl8188E\\radio_a_1T.txt"
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#define RTL8188E_PHY_RADIO_B "rtl8188E\\radio_b_1T.txt"
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#define RTL8188E_AGC_TAB "rtl8188E\\AGC_TAB_1T.txt"
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#define RTL8188E_PHY_MACREG "rtl8188E\\MAC_REG.txt"
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#define RTL8188E_PHY_REG_PG "rtl8188E\\PHY_REG_PG.txt"
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#define RTL8188E_PHY_REG_MP "rtl8188E\\PHY_REG_MP.txt"
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/* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
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#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
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#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
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#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
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#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
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#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
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#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
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#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
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#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
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#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
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#define DRVINFO_SZ 4 /* unit is 8bytes */
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#define PageNum_128(_Len) (u32)(((_Len) >> 7) + ((_Len) & 0x7F ? 1 : 0))
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/* download firmware related data structure */
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#define FW_8188E_SIZE 0x4000 /* 16384,16k */
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#define FW_8188E_START_ADDRESS 0x1000
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#define FW_8188E_END_ADDRESS 0x1FFF /* 0x5FFF */
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#define MAX_PAGE_SIZE 4096 /* @ page : 4k bytes */
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#define IS_FW_HEADER_EXIST(_pFwHdr) \
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((le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x92C0 || \
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(le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x88C0 || \
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(le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x2300 || \
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(le16_to_cpu(_pFwHdr->signature) & 0xFFF0) == 0x88E0)
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#define DRIVER_EARLY_INT_TIME 0x05
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#define BCN_DMA_ATIME_INT_TIME 0x02
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enum usb_rx_agg_mode {
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USB_RX_AGG_DISABLE,
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USB_RX_AGG_DMA,
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USB_RX_AGG_USB,
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USB_RX_AGG_MIX
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};
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#define MAX_RX_DMA_BUFFER_SIZE_88E \
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0x2400 /* 9k for 88E nornal chip , MaxRxBuff=10k-max(TxReportSize(64*8),
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* WOLPattern(16*24))
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*/
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#define MAX_TX_REPORT_BUFFER_SIZE 0x0400 /* 1k */
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/* BK, BE, VI, VO, HCCA, MANAGEMENT, COMMAND, HIGH, BEACON. */
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#define MAX_TX_QUEUE 9
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#define TX_SELE_HQ BIT(0) /* High Queue */
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#define TX_SELE_LQ BIT(1) /* Low Queue */
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#define TX_SELE_NQ BIT(2) /* Normal Queue */
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/* Note: We will divide number of page equally for each queue other
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* than public queue!
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*/
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/* 22k = 22528 bytes = 176 pages (@page = 128 bytes) */
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/* must reserved about 7 pages for LPS => 176-7 = 169 (0xA9) */
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/* 2*BCN / 1*ps-poll / 1*null-data /1*prob_rsp /1*QOS null-data /1*BT QOS
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* null-data
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*/
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#define TX_TOTAL_PAGE_NUMBER_88E 0xA9/* 169 (21632=> 21k) */
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#define TX_PAGE_BOUNDARY_88E (TX_TOTAL_PAGE_NUMBER_88E + 1)
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/* Note: For Normal Chip Setting ,modify later */
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#define WMM_NORMAL_TX_TOTAL_PAGE_NUMBER \
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TX_TOTAL_PAGE_NUMBER_88E /* 0xA9 , 0xb0=>176=>22k */
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#define WMM_NORMAL_TX_PAGE_BOUNDARY_88E \
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(WMM_NORMAL_TX_TOTAL_PAGE_NUMBER + 1) /* 0xA9 */
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/* Chip specific */
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#define CHIP_BONDING_IDENTIFIER(_value) (((_value) >> 22) & 0x3)
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#define CHIP_BONDING_92C_1T2R 0x1
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#define CHIP_BONDING_88C_USB_MCARD 0x2
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#define CHIP_BONDING_88C_USB_HP 0x1
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#include "HalVerDef.h"
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#include "hal_com.h"
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/* Channel Plan */
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enum ChannelPlan {
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CHPL_FCC = 0,
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CHPL_IC = 1,
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CHPL_ETSI = 2,
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CHPL_SPA = 3,
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CHPL_FRANCE = 4,
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CHPL_MKK = 5,
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CHPL_MKK1 = 6,
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CHPL_ISRAEL = 7,
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CHPL_TELEC = 8,
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CHPL_GLOBAL = 9,
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CHPL_WORLD = 10,
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};
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struct txpowerinfo24g {
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u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
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u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
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/* If only one tx, only BW20 and OFDM are used. */
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s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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};
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#define EFUSE_REAL_CONTENT_LEN 512
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#define EFUSE_MAX_SECTION 16
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#define EFUSE_IC_ID_OFFSET 506 /* For some inferior IC purpose*/
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#define AVAILABLE_EFUSE_ADDR(addr) (addr < EFUSE_REAL_CONTENT_LEN)
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/* To prevent out of boundary programming case, */
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/* leave 1byte and program full section */
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/* 9bytes + 1byt + 5bytes and pre 1byte. */
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/* For worst case: */
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/* | 1byte|----8bytes----|1byte|--5bytes--| */
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/* | | Reserved(14bytes) | */
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/* PG data exclude header, dummy 6 bytes from CP test and reserved 1byte. */
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#define EFUSE_OOB_PROTECT_BYTES 15
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#define HWSET_MAX_SIZE_88E 512
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#define EFUSE_REAL_CONTENT_LEN_88E 256
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#define EFUSE_MAP_LEN_88E 512
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#define EFUSE_MAP_LEN EFUSE_MAP_LEN_88E
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#define EFUSE_MAX_SECTION_88E 64
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#define EFUSE_MAX_WORD_UNIT_88E 4
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#define EFUSE_IC_ID_OFFSET_88E 506
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#define AVAILABLE_EFUSE_ADDR_88E(addr) \
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(addr < EFUSE_REAL_CONTENT_LEN_88E)
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/* To prevent out of boundary programming case, leave 1byte and program
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* full section
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*/
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/* 9bytes + 1byt + 5bytes and pre 1byte. */
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/* For worst case: */
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/* | 2byte|----8bytes----|1byte|--7bytes--| 92D */
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/* PG data exclude header, dummy 7 bytes from CP test and reserved 1byte. */
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#define EFUSE_OOB_PROTECT_BYTES_88E 18
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#define EFUSE_PROTECT_BYTES_BANK_88E 16
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/* EFUSE for BT definition */
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#define EFUSE_BT_REAL_CONTENT_LEN 1536 /* 512*3 */
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#define EFUSE_BT_MAP_LEN 1024 /* 1k bytes */
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#define EFUSE_BT_MAX_SECTION 128 /* 1024/8 */
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#define EFUSE_PROTECT_BYTES_BANK 16
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struct hal_data_8188e {
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struct HAL_VERSION VersionID;
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u16 CustomerID;
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u16 FirmwareVersion;
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u16 FirmwareVersionRev;
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u16 FirmwareSubVersion;
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u16 FirmwareSignature;
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u8 PGMaxGroup;
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/* current WIFI_PHY values */
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u32 ReceiveConfig;
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enum wireless_mode CurrentWirelessMode;
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enum ht_channel_width CurrentChannelBW;
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u8 CurrentChannel;
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u8 nCur40MhzPrimeSC;/* Control channel sub-carrier */
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u16 BasicRateSet;
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u8 BoardType;
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/* EEPROM setting. */
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u16 EEPROMVID;
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u16 EEPROMPID;
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u16 EEPROMSVID;
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u16 EEPROMSDID;
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u8 EEPROMCustomerID;
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u8 EEPROMSubCustomerID;
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u8 EEPROMVersion;
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u8 EEPROMRegulatory;
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u8 bTXPowerDataReadFromEEPORM;
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u8 EEPROMThermalMeter;
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u8 bAPKThermalMeterIgnore;
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bool EepromOrEfuse;
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/* 92C:256bytes, 88E:512bytes, we use union set (512bytes) */
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u8 EfuseMap[2][HWSET_MAX_SIZE_512];
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u8 EfuseUsedPercentage;
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struct efuse_hal EfuseHal;
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u8 Index24G_CCK_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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u8 Index24G_BW40_Base[MAX_RF_PATH][CHANNEL_MAX_NUMBER];
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/* If only one tx, only BW20 and OFDM are used. */
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s8 CCK_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 OFDM_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW20_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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s8 BW40_24G_Diff[MAX_RF_PATH][MAX_TX_COUNT];
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u8 TxPwrLevelCck[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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/* For HT 40MHZ pwr */
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u8 TxPwrLevelHT40_1S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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/* For HT 40MHZ pwr */
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u8 TxPwrLevelHT40_2S[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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/* HT 20<->40 Pwr diff */
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u8 TxPwrHt20Diff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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/* For HT<->legacy pwr diff */
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u8 TxPwrLegacyHtDiff[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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/* For power group */
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u8 PwrGroupHT20[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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u8 PwrGroupHT40[RF_PATH_MAX][CHANNEL_MAX_NUMBER];
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u8 LegacyHTTxPowerDiff;/* Legacy to HT rate power diff */
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/* The current Tx Power Level */
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u8 CurrentCckTxPwrIdx;
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u8 CurrentOfdm24GTxPwrIdx;
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u8 CurrentBW2024GTxPwrIdx;
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u8 CurrentBW4024GTxPwrIdx;
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/* Read/write are allow for following hardware information variables */
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u8 framesync;
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u32 framesyncC34;
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u8 framesyncMonitor;
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u8 DefaultInitialGain[4];
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u8 pwrGroupCnt;
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u32 MCSTxPowerLevelOriginalOffset[MAX_PG_GROUP][16];
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u32 CCKTxPowerLevelOriginalOffset;
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u8 CrystalCap;
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u32 AcParam_BE; /* Original parameter for BE, use for EDCA turbo. */
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struct bb_reg_def PHYRegDef[4]; /* Radio A/B/C/D */
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u32 RfRegChnlVal[2];
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/* RDG enable */
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bool bRDGEnable;
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/* for host message to fw */
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u8 LastHMEBoxNum;
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u8 RegTxPause;
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/* Beacon function related global variable. */
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u32 RegBcnCtrlVal;
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u8 RegFwHwTxQCtrl;
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u8 RegReg542;
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u8 RegCR_1;
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struct dm_priv dmpriv;
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struct odm_dm_struct odmpriv;
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struct sreset_priv srestpriv;
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u8 CurAntenna;
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u8 AntDivCfg;
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u8 TRxAntDivType;
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u8 bDumpRxPkt;/* for debug */
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u8 bDumpTxPkt;/* for debug */
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u8 FwRsvdPageStartOffset; /* Reserve page start offset except
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* beacon in TxQ.
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*/
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/* 2010/08/09 MH Add CU power down mode. */
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bool pwrdown;
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/* Add for dual MAC 0--Mac0 1--Mac1 */
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u32 interfaceIndex;
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u8 OutEpQueueSel;
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u8 OutEpNumber;
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u16 EfuseUsedBytes;
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/* Auto FSM to Turn On, include clock, isolation, power control
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* for MAC only
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*/
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u8 bMacPwrCtrlOn;
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u32 UsbBulkOutSize;
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/* Interrupt relatd register information. */
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u32 IntArray[3];/* HISR0,HISR1,HSISR */
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u32 IntrMask[3];
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u8 C2hArray[16];
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u8 UsbTxAggMode;
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u8 UsbTxAggDescNum;
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u16 HwRxPageSize; /* Hardware setting */
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u32 MaxUsbRxAggBlock;
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enum usb_rx_agg_mode UsbRxAggMode;
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u8 UsbRxAggBlockCount; /* USB Block count. Block size is
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* 512-byte in high speed and 64-byte
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* in full speed
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*/
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u8 UsbRxAggBlockTimeout;
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u8 UsbRxAggPageCount; /* 8192C DMA page count */
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u8 UsbRxAggPageTimeout;
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};
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void Hal_GetChnlGroup88E(u8 chnl, u8 *group);
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/* rtl8188e_hal_init.c */
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void _8051Reset88E(struct adapter *padapter);
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void rtl8188e_InitializeFirmwareVars(struct adapter *padapter);
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s32 InitLLTTable(struct adapter *padapter, u8 txpktbuf_bndy);
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/* EFuse */
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void Hal_InitPGData88E(struct adapter *padapter);
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void Hal_EfuseParseIDCode88E(struct adapter *padapter, u8 *hwinfo);
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void Hal_ReadTxPowerInfo88E(struct adapter *padapter, u8 *hwinfo,
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bool AutoLoadFail);
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void Hal_EfuseParseEEPROMVer88E(struct adapter *padapter, u8 *hwinfo,
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bool AutoLoadFail);
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void rtl8188e_EfuseParseChnlPlan(struct adapter *padapter, u8 *hwinfo,
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bool AutoLoadFail);
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void Hal_EfuseParseCustomerID88E(struct adapter *padapter, u8 *hwinfo,
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bool AutoLoadFail);
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void Hal_ReadAntennaDiversity88E(struct adapter *pAdapter, u8 *PROMContent,
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bool AutoLoadFail);
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void Hal_ReadThermalMeter_88E(struct adapter *dapter, u8 *PROMContent,
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bool AutoloadFail);
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void Hal_EfuseParseXtal_8188E(struct adapter *pAdapter, u8 *hwinfo,
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bool AutoLoadFail);
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void Hal_EfuseParseBoardType88E(struct adapter *pAdapter, u8 *hwinfo,
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bool AutoLoadFail);
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void Hal_ReadPowerSavingMode88E(struct adapter *pAdapter, u8 *hwinfo,
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bool AutoLoadFail);
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/* register */
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void rtl8188e_start_thread(struct adapter *padapter);
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void rtl8188e_stop_thread(struct adapter *padapter);
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s32 iol_execute(struct adapter *padapter, u8 control);
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void iol_mode_enable(struct adapter *padapter, u8 enable);
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s32 rtl8188e_iol_efuse_patch(struct adapter *padapter);
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void rtw_cancel_all_timer(struct adapter *padapter);
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#endif /* __RTL8188E_HAL_H__ */
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