/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#ifndef __HAL8188EPWRSEQ_H__
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#define __HAL8188EPWRSEQ_H__
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#include "pwrseqcmd.h"
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/*
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* Check document WM-20110607-Paul-RTL8188E_Power_Architecture-R02.vsd
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* There are 6 HW Power States:
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* 0: POFF--Power Off
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* 1: PDN--Power Down
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* 2: CARDEMU--Card Emulation
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* 3: ACT--Active Mode
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* 4: LPS--Low Power State
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* 5: SUS--Suspend
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*
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* The transition from different states are defined below
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* TRANS_CARDEMU_TO_ACT
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* TRANS_ACT_TO_CARDEMU
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* TRANS_CARDEMU_TO_SUS
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* TRANS_SUS_TO_CARDEMU
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* TRANS_CARDEMU_TO_PDN
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* TRANS_ACT_TO_LPS
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* TRANS_LPS_TO_ACT
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*
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* TRANS_END
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*
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* PWR SEQ Version: rtl8188E_PwrSeq_V09.h
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*/
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#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
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#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
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#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
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#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
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#define RTL8188E_TRANS_END_STEPS 1
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#define RTL8188E_TRANS_CARDEMU_TO_ACT \
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/* format
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* { offset, cut_msk, cmd, msk, value
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* },
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* comment here
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*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
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/* wait till 0x04[17] = 1 power ready*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
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/* 0x02[1:0] = 0 reset BB*/ \
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{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
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/* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
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/*0x04[12:11] = 2b'00 disable WL suspend*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
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/*0x04[8] = 1 polling until return 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(0), 0}, \
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/*wait till 0x04[8] = 0*/ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/*LDO normal mode*/
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#define RTL8188E_TRANS_ACT_TO_CARDEMU \
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/* format
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* { offset, cut_msk, cmd, msk, value
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* },
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* comments here
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*/ \
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{0x001F, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
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/*0x1F[7:0] = 0 turn off RF*/ \
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{0x0023, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*LDO Sleep mode*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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/*0x04[9] = 1 turn off MAC by HW state machine*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \
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/*wait till 0x04[9] = 0 polling until return 0 to disable*/
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#define RTL8188E_TRANS_CARDEMU_TO_SUS \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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/* 0x04[12:11] = 2b'01enable WL suspend */ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \
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/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
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{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */
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#define RTL8188E_TRANS_SUS_TO_CARDEMU \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
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/*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0026, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/*0x24[23] = 2b'01 schmit trigger */ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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/*0x04[12:11] = 2b'01 enable WL suspend*/ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, \
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/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
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{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */
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#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
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/*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_PDN \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
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/* 0x04[16] = 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/* 0x04[15] = 1*/
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#define RTL8188E_TRANS_PDN_TO_CARDEMU \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
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/* 0x04[15] = 0*/
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/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
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#define RTL8188E_TRANS_ACT_TO_LPS \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x7F},/*Tx Pause*/ \
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{0x05F8, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05F9, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05FA, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x05FB, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, 0xFF, 0}, \
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/*Should be zero if no packet is transmitting*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
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/*CCK and OFDM are disabled,and clock are gated*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_US}, \
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/*Delay 1us*/ \
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{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x3F}, \
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/*Reset MAC TRX*/ \
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{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), 0}, \
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/*check if removed later*/\
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{0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
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/*Respond TxOK to scheduler*/
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#define RTL8188E_TRANS_LPS_TO_ACT \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0xFE58, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x84}, \
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/*USB RPWM*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
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/*Delay*/ \
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{0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/* 0x08[4] = 0 switch TSF to 40M */ \
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{0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \
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/* Polling 0x109[7]=0 TSF in 40M */ \
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{0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \
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/* 0x29[7:6] = 2b'00 enable BB clock */ \
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{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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/* 0x101[1] = 1 */ \
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{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0xFF}, \
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/* 0x100[7:0] = 0xFF enable WMAC TRX */ \
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{0x0002, PWR_CUT_ALL_MSK, \
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PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
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/* 0x02[1:0] = 2b'11 enable BB macro */ \
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{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
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#define RTL8188E_TRANS_END \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0xFFFF, PWR_CUT_ALL_MSK, PWR_CMD_END, 0, 0},
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extern struct wl_pwr_cfg rtl8188E_power_on_flow
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[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_radio_off_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_card_disable_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_card_enable_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_suspend_flow[
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RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
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RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_resume_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
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RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_hwpdn_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_enter_lps_flow
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[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_leave_lps_flow
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[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
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#endif /* __HAL8188EPWRSEQ_H__ */
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