/* SPDX-License-Identifier: GPL-2.0 */
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#ifndef __HALHWOUTSRC_H__
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#define __HALHWOUTSRC_H__
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/* Definition */
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/* CCK Rates, TxHT = 0 */
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#define DESC92C_RATE1M 0x00
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#define DESC92C_RATE2M 0x01
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#define DESC92C_RATE5_5M 0x02
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#define DESC92C_RATE11M 0x03
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/* OFDM Rates, TxHT = 0 */
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#define DESC92C_RATE6M 0x04
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#define DESC92C_RATE9M 0x05
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#define DESC92C_RATE12M 0x06
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#define DESC92C_RATE18M 0x07
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#define DESC92C_RATE24M 0x08
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#define DESC92C_RATE36M 0x09
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#define DESC92C_RATE48M 0x0a
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#define DESC92C_RATE54M 0x0b
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/* MCS Rates, TxHT = 1 */
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#define DESC92C_RATEMCS0 0x0c
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#define DESC92C_RATEMCS1 0x0d
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#define DESC92C_RATEMCS2 0x0e
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#define DESC92C_RATEMCS3 0x0f
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#define DESC92C_RATEMCS4 0x10
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#define DESC92C_RATEMCS5 0x11
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#define DESC92C_RATEMCS6 0x12
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#define DESC92C_RATEMCS7 0x13
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#define DESC92C_RATEMCS8 0x14
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#define DESC92C_RATEMCS9 0x15
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#define DESC92C_RATEMCS10 0x16
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#define DESC92C_RATEMCS11 0x17
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#define DESC92C_RATEMCS12 0x18
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#define DESC92C_RATEMCS13 0x19
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#define DESC92C_RATEMCS14 0x1a
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#define DESC92C_RATEMCS15 0x1b
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#define DESC92C_RATEMCS15_SG 0x1c
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#define DESC92C_RATEMCS32 0x20
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/* structure and define */
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struct phy_rx_agc_info {
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#ifdef __LITTLE_ENDIAN
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u8 gain:7, trsw:1;
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#else
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u8 trsw:1, gain:7;
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#endif
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};
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struct phy_status_rpt {
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struct phy_rx_agc_info path_agc[RF_PATH_MAX];
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u8 ch_corr[2];
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u8 cck_sig_qual_ofdm_pwdb_all;
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u8 cck_agc_rpt_ofdm_cfosho_a;
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u8 cck_rpt_b_ofdm_cfosho_b;
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u8 rsvd_1;/* ch_corr_msb; */
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u8 noise_power_db_msb;
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u8 path_cfotail[2];
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u8 pcts_mask[2];
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s8 stream_rxevm[2];
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u8 path_rxsnr[3];
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u8 noise_power_db_lsb;
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u8 rsvd_2[3];
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u8 stream_csi[2];
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u8 stream_target_csi[2];
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s8 sig_evm;
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u8 rsvd_3;
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#ifdef __LITTLE_ENDIAN
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u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
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u8 sgi_en:1;
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u8 rxsc:2;
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u8 idle_long:1;
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u8 r_ant_train_en:1;
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u8 ant_sel_b:1;
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u8 ant_sel:1;
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#else /* _BIG_ENDIAN_ */
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u8 ant_sel:1;
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u8 ant_sel_b:1;
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u8 r_ant_train_en:1;
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u8 idle_long:1;
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u8 rxsc:2;
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u8 sgi_en:1;
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u8 antsel_rx_keep_2:1; /* ex_intf_flg:1; */
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#endif
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};
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void ODM_PhyStatusQuery(struct odm_dm_struct *pDM_Odm,
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struct odm_phy_status_info *pPhyInfo,
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u8 *pPhyStatus,
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struct odm_per_pkt_info *pPktinfo);
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#endif
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