// SPDX-License-Identifier: GPL-2.0
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/******************************************************************************
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*
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* Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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*
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******************************************************************************/
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#include <osdep_service.h>
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#include <drv_types.h>
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#include <phy.h>
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#include <rf.h>
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#include <rtl8188e_hal.h>
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void rtl88eu_phy_rf6052_set_bandwidth(struct adapter *adapt,
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enum ht_channel_width bandwidth)
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{
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struct hal_data_8188e *hal_data = adapt->HalData;
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switch (bandwidth) {
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case HT_CHANNEL_WIDTH_20:
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hal_data->RfRegChnlVal[0] = ((hal_data->RfRegChnlVal[0] &
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0xfffff3ff) | BIT(10) | BIT(11));
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phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,
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hal_data->RfRegChnlVal[0]);
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break;
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case HT_CHANNEL_WIDTH_40:
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hal_data->RfRegChnlVal[0] = ((hal_data->RfRegChnlVal[0] &
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0xfffff3ff) | BIT(10));
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phy_set_rf_reg(adapt, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,
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hal_data->RfRegChnlVal[0]);
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break;
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default:
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break;
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}
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}
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void rtl88eu_phy_rf6052_set_cck_txpower(struct adapter *adapt, u8 *powerlevel)
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{
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struct hal_data_8188e *hal_data = adapt->HalData;
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struct dm_priv *pdmpriv = &hal_data->dmpriv;
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struct mlme_ext_priv *pmlmeext = &adapt->mlmeextpriv;
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u32 tx_agc[2] = {0, 0}, tmpval = 0, pwrtrac_value;
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u8 idx1, idx2;
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u8 *ptr;
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u8 direction;
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if (pmlmeext->sitesurvey_res.state == SCAN_PROCESS) {
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tx_agc[RF_PATH_A] = 0x3f3f3f3f;
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tx_agc[RF_PATH_B] = 0x3f3f3f3f;
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for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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tx_agc[idx1] = powerlevel[idx1] |
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(powerlevel[idx1] << 8) |
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(powerlevel[idx1] << 16) |
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(powerlevel[idx1] << 24);
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}
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} else {
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1) {
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tx_agc[RF_PATH_A] = 0x10101010;
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tx_agc[RF_PATH_B] = 0x10101010;
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} else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2) {
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tx_agc[RF_PATH_A] = 0x00000000;
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tx_agc[RF_PATH_B] = 0x00000000;
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} else {
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for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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tx_agc[idx1] = powerlevel[idx1] |
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(powerlevel[idx1] << 8) |
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(powerlevel[idx1] << 16) |
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(powerlevel[idx1] << 24);
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}
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if (hal_data->EEPROMRegulatory == 0) {
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tmpval = hal_data->MCSTxPowerLevelOriginalOffset[0][6] +
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(hal_data->MCSTxPowerLevelOriginalOffset[0][7] << 8);
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tx_agc[RF_PATH_A] += tmpval;
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tmpval = hal_data->MCSTxPowerLevelOriginalOffset[0][14] +
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(hal_data->MCSTxPowerLevelOriginalOffset[0][15] << 24);
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tx_agc[RF_PATH_B] += tmpval;
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}
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}
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}
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for (idx1 = RF_PATH_A; idx1 <= RF_PATH_B; idx1++) {
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ptr = (u8 *)(&tx_agc[idx1]);
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for (idx2 = 0; idx2 < 4; idx2++) {
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if (*ptr > RF6052_MAX_TX_PWR)
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*ptr = RF6052_MAX_TX_PWR;
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ptr++;
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}
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}
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rtl88eu_dm_txpower_track_adjust(&hal_data->odmpriv, 1, &direction,
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&pwrtrac_value);
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if (direction == 1) {
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/* Increase TX power */
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tx_agc[0] += pwrtrac_value;
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tx_agc[1] += pwrtrac_value;
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} else if (direction == 2) {
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/* Decrease TX power */
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tx_agc[0] -= pwrtrac_value;
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tx_agc[1] -= pwrtrac_value;
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}
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/* rf-A cck tx power */
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tmpval = tx_agc[RF_PATH_A] & 0xff;
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phy_set_bb_reg(adapt, rTxAGC_A_CCK1_Mcs32, bMaskByte1, tmpval);
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tmpval = tx_agc[RF_PATH_A] >> 8;
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phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
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/* rf-B cck tx power */
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tmpval = tx_agc[RF_PATH_B] >> 24;
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phy_set_bb_reg(adapt, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte0, tmpval);
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tmpval = tx_agc[RF_PATH_B] & 0x00ffffff;
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phy_set_bb_reg(adapt, rTxAGC_B_CCK1_55_Mcs32, 0xffffff00, tmpval);
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}
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/* powerbase0 for OFDM rates */
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/* powerbase1 for HT MCS rates */
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static void getpowerbase88e(struct adapter *adapt, u8 *pwr_level_ofdm,
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u8 *pwr_level_bw20, u8 *pwr_level_bw40,
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u8 channel, u32 *ofdmbase, u32 *mcs_base)
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{
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u32 powerbase0, powerbase1;
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u8 i, powerlevel[2];
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for (i = 0; i < 2; i++) {
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powerbase0 = pwr_level_ofdm[i];
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powerbase0 = (powerbase0 << 24) | (powerbase0 << 16) |
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(powerbase0 << 8) | powerbase0;
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*(ofdmbase + i) = powerbase0;
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}
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/* Check HT20 to HT40 diff */
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if (adapt->HalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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powerlevel[0] = pwr_level_bw20[0];
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else
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powerlevel[0] = pwr_level_bw40[0];
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powerbase1 = powerlevel[0];
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powerbase1 = (powerbase1 << 24) | (powerbase1 << 16) |
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(powerbase1 << 8) | powerbase1;
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*mcs_base = powerbase1;
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}
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static void get_rx_power_val_by_reg(struct adapter *adapt, u8 channel,
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u8 index, u32 *powerbase0, u32 *powerbase1,
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u32 *out_val)
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{
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struct hal_data_8188e *hal_data = adapt->HalData;
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struct dm_priv *pdmpriv = &hal_data->dmpriv;
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u8 i, chnlGroup = 0, pwr_diff_limit[4], customer_pwr_limit;
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s8 pwr_diff = 0;
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u32 write_val, customer_limit, rf;
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u8 regulatory = hal_data->EEPROMRegulatory;
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/* Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate */
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for (rf = 0; rf < 2; rf++) {
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u8 j = index + (rf ? 8 : 0);
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switch (regulatory) {
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case 0:
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chnlGroup = 0;
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write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] +
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((index < 2) ? powerbase0[rf] : powerbase1[rf]);
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break;
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case 1: /* Realtek regulatory */
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/* increase power diff defined by Realtek for regulatory */
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if (hal_data->pwrGroupCnt == 1)
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chnlGroup = 0;
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if (hal_data->pwrGroupCnt >= hal_data->PGMaxGroup)
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Hal_GetChnlGroup88E(channel, &chnlGroup);
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write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][index + (rf ? 8 : 0)] +
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((index < 2) ? powerbase0[rf] : powerbase1[rf]);
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break;
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case 2: /* Better regulatory */
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/* don't increase any power diff */
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write_val = (index < 2) ? powerbase0[rf] : powerbase1[rf];
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break;
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case 3: /* Customer defined power diff. */
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/* increase power diff defined by customer. */
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chnlGroup = 0;
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if (index < 2)
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pwr_diff = hal_data->TxPwrLegacyHtDiff[rf][channel - 1];
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else if (hal_data->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
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pwr_diff = hal_data->TxPwrHt20Diff[rf][channel - 1];
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if (hal_data->CurrentChannelBW == HT_CHANNEL_WIDTH_40)
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customer_pwr_limit = hal_data->PwrGroupHT40[rf][channel - 1];
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else
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customer_pwr_limit = hal_data->PwrGroupHT20[rf][channel - 1];
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if (pwr_diff >= customer_pwr_limit)
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pwr_diff = 0;
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else
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pwr_diff = customer_pwr_limit - pwr_diff;
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for (i = 0; i < 4; i++) {
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pwr_diff_limit[i] = (u8)((hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][j] &
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(0x7f << (i * 8))) >> (i * 8));
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if (pwr_diff_limit[i] > pwr_diff)
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pwr_diff_limit[i] = pwr_diff;
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}
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customer_limit = (pwr_diff_limit[3] << 24) |
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(pwr_diff_limit[2] << 16) |
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(pwr_diff_limit[1] << 8) |
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(pwr_diff_limit[0]);
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write_val = customer_limit + ((index < 2) ? powerbase0[rf] : powerbase1[rf]);
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break;
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default:
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chnlGroup = 0;
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write_val = hal_data->MCSTxPowerLevelOriginalOffset[chnlGroup][j] +
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((index < 2) ? powerbase0[rf] : powerbase1[rf]);
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break;
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}
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/* 20100427 Joseph: Driver dynamic Tx power shall not affect Tx power. It shall be determined by power training mechanism. */
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/* Currently, we cannot fully disable driver dynamic tx power mechanism because it is referenced by BT coexist mechanism. */
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/* In the future, two mechanism shall be separated from each other and maintained independently. Thanks for Lanhsin's reminder. */
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/* 92d do not need this */
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if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
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write_val = 0x14141414;
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else if (pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
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write_val = 0x00000000;
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*(out_val + rf) = write_val;
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}
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}
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static void write_ofdm_pwr_reg(struct adapter *adapt, u8 index, u32 *pvalue)
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{
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u16 regoffset_a[6] = { rTxAGC_A_Rate18_06, rTxAGC_A_Rate54_24,
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rTxAGC_A_Mcs03_Mcs00, rTxAGC_A_Mcs07_Mcs04,
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rTxAGC_A_Mcs11_Mcs08, rTxAGC_A_Mcs15_Mcs12 };
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u16 regoffset_b[6] = { rTxAGC_B_Rate18_06, rTxAGC_B_Rate54_24,
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rTxAGC_B_Mcs03_Mcs00, rTxAGC_B_Mcs07_Mcs04,
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rTxAGC_B_Mcs11_Mcs08, rTxAGC_B_Mcs15_Mcs12 };
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u8 i, rf, pwr_val[4];
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u32 write_val;
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u16 regoffset;
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for (rf = 0; rf < 2; rf++) {
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write_val = pvalue[rf];
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for (i = 0; i < 4; i++) {
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pwr_val[i] = (u8)((write_val & (0x7f << (i * 8))) >> (i * 8));
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if (pwr_val[i] > RF6052_MAX_TX_PWR)
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pwr_val[i] = RF6052_MAX_TX_PWR;
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}
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write_val = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
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(pwr_val[1] << 8) | pwr_val[0];
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if (rf == 0)
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regoffset = regoffset_a[index];
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else
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regoffset = regoffset_b[index];
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phy_set_bb_reg(adapt, regoffset, bMaskDWord, write_val);
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}
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}
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void rtl88eu_phy_rf6052_set_ofdm_txpower(struct adapter *adapt,
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u8 *pwr_level_ofdm,
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u8 *pwr_level_bw20,
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u8 *pwr_level_bw40, u8 channel)
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{
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u32 write_val[2], powerbase0[2], powerbase1[2], pwrtrac_value;
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u8 direction;
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u8 index = 0;
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getpowerbase88e(adapt, pwr_level_ofdm, pwr_level_bw20, pwr_level_bw40,
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channel, &powerbase0[0], &powerbase1[0]);
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rtl88eu_dm_txpower_track_adjust(&adapt->HalData->odmpriv, 0,
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&direction, &pwrtrac_value);
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for (index = 0; index < 6; index++) {
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get_rx_power_val_by_reg(adapt, channel, index,
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&powerbase0[0], &powerbase1[0],
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&write_val[0]);
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if (direction == 1) {
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write_val[0] += pwrtrac_value;
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write_val[1] += pwrtrac_value;
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} else if (direction == 2) {
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write_val[0] -= pwrtrac_value;
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write_val[1] -= pwrtrac_value;
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}
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write_ofdm_pwr_reg(adapt, index, &write_val[0]);
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}
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}
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