// SPDX-License-Identifier: GPL-2.0
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/*
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* dim2.c - MediaLB DIM2 Hardware Dependent Module
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*
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* Copyright (C) 2015-2016, Microchip Technology Germany II GmbH & Co. KG
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/module.h>
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#include <linux/of_platform.h>
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#include <linux/printk.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/sched.h>
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#include <linux/kthread.h>
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#include <linux/most.h>
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#include "hal.h"
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#include "errors.h"
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#include "sysfs.h"
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#define DMA_CHANNELS (32 - 1) /* channel 0 is a system channel */
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#define MAX_BUFFERS_PACKET 32
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#define MAX_BUFFERS_STREAMING 32
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#define MAX_BUF_SIZE_PACKET 2048
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#define MAX_BUF_SIZE_STREAMING (8 * 1024)
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/*
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* The parameter representing the number of frames per sub-buffer for
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* synchronous channels. Valid values: [0 .. 6].
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*
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* The values 0, 1, 2, 3, 4, 5, 6 represent corresponding number of frames per
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* sub-buffer 1, 2, 4, 8, 16, 32, 64.
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*/
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static u8 fcnt = 4; /* (1 << fcnt) frames per subbuffer */
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module_param(fcnt, byte, 0000);
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MODULE_PARM_DESC(fcnt, "Num of frames per sub-buffer for sync channels as a power of 2");
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static DEFINE_SPINLOCK(dim_lock);
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static void dim2_tasklet_fn(unsigned long data);
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static DECLARE_TASKLET_OLD(dim2_tasklet, dim2_tasklet_fn);
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/**
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* struct hdm_channel - private structure to keep channel specific data
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* @is_initialized: identifier to know whether the channel is initialized
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* @ch: HAL specific channel data
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* @pending_list: list to keep MBO's before starting transfer
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* @started_list: list to keep MBO's after starting transfer
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* @direction: channel direction (TX or RX)
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* @data_type: channel data type
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*/
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struct hdm_channel {
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char name[sizeof "caNNN"];
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bool is_initialized;
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struct dim_channel ch;
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u16 *reset_dbr_size;
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struct list_head pending_list; /* before dim_enqueue_buffer() */
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struct list_head started_list; /* after dim_enqueue_buffer() */
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enum most_channel_direction direction;
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enum most_channel_data_type data_type;
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};
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/**
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* struct dim2_hdm - private structure to keep interface specific data
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* @hch: an array of channel specific data
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* @most_iface: most interface structure
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* @capabilities: an array of channel capability data
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* @io_base: I/O register base address
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* @netinfo_task: thread to deliver network status
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* @netinfo_waitq: waitq for the thread to sleep
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* @deliver_netinfo: to identify whether network status received
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* @mac_addrs: INIC mac address
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* @link_state: network link state
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* @atx_idx: index of async tx channel
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*/
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struct dim2_hdm {
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struct device dev;
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struct hdm_channel hch[DMA_CHANNELS];
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struct most_channel_capability capabilities[DMA_CHANNELS];
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struct most_interface most_iface;
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char name[16 + sizeof "dim2-"];
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void __iomem *io_base;
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u8 clk_speed;
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struct clk *clk;
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struct clk *clk_pll;
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struct task_struct *netinfo_task;
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wait_queue_head_t netinfo_waitq;
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int deliver_netinfo;
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unsigned char mac_addrs[6];
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unsigned char link_state;
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int atx_idx;
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struct medialb_bus bus;
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void (*on_netinfo)(struct most_interface *most_iface,
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unsigned char link_state, unsigned char *addrs);
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void (*disable_platform)(struct platform_device *pdev);
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};
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struct dim2_platform_data {
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int (*enable)(struct platform_device *pdev);
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void (*disable)(struct platform_device *pdev);
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};
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#define iface_to_hdm(iface) container_of(iface, struct dim2_hdm, most_iface)
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/* Macro to identify a network status message */
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#define PACKET_IS_NET_INFO(p) \
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(((p)[1] == 0x18) && ((p)[2] == 0x05) && ((p)[3] == 0x0C) && \
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((p)[13] == 0x3C) && ((p)[14] == 0x00) && ((p)[15] == 0x0A))
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static ssize_t state_show(struct device *dev, struct device_attribute *attr,
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char *buf)
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{
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bool state;
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unsigned long flags;
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spin_lock_irqsave(&dim_lock, flags);
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state = dim_get_lock_state();
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spin_unlock_irqrestore(&dim_lock, flags);
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return sysfs_emit(buf, "%s\n", state ? "locked" : "");
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}
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static DEVICE_ATTR_RO(state);
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static struct attribute *dim2_attrs[] = {
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&dev_attr_state.attr,
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NULL,
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};
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ATTRIBUTE_GROUPS(dim2);
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/**
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* dimcb_on_error - callback from HAL to report miscommunication between
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* HDM and HAL
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* @error_id: Error ID
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* @error_message: Error message. Some text in a free format
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*/
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void dimcb_on_error(u8 error_id, const char *error_message)
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{
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pr_err("%s: error_id - %d, error_message - %s\n", __func__, error_id,
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error_message);
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}
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/**
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* try_start_dim_transfer - try to transfer a buffer on a channel
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* @hdm_ch: channel specific data
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*
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* Transfer a buffer from pending_list if the channel is ready
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*/
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static int try_start_dim_transfer(struct hdm_channel *hdm_ch)
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{
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u16 buf_size;
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struct list_head *head = &hdm_ch->pending_list;
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struct mbo *mbo;
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unsigned long flags;
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struct dim_ch_state_t st;
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BUG_ON(!hdm_ch);
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BUG_ON(!hdm_ch->is_initialized);
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spin_lock_irqsave(&dim_lock, flags);
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if (list_empty(head)) {
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spin_unlock_irqrestore(&dim_lock, flags);
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return -EAGAIN;
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}
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if (!dim_get_channel_state(&hdm_ch->ch, &st)->ready) {
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spin_unlock_irqrestore(&dim_lock, flags);
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return -EAGAIN;
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}
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mbo = list_first_entry(head, struct mbo, list);
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buf_size = mbo->buffer_length;
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if (dim_dbr_space(&hdm_ch->ch) < buf_size) {
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spin_unlock_irqrestore(&dim_lock, flags);
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return -EAGAIN;
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}
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BUG_ON(mbo->bus_address == 0);
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if (!dim_enqueue_buffer(&hdm_ch->ch, mbo->bus_address, buf_size)) {
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list_del(head->next);
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spin_unlock_irqrestore(&dim_lock, flags);
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mbo->processed_length = 0;
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mbo->status = MBO_E_INVAL;
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mbo->complete(mbo);
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return -EFAULT;
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}
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list_move_tail(head->next, &hdm_ch->started_list);
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spin_unlock_irqrestore(&dim_lock, flags);
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return 0;
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}
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/**
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* deliver_netinfo_thread - thread to deliver network status to mostcore
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* @data: private data
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*
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* Wait for network status and deliver it to mostcore once it is received
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*/
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static int deliver_netinfo_thread(void *data)
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{
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struct dim2_hdm *dev = data;
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while (!kthread_should_stop()) {
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wait_event_interruptible(dev->netinfo_waitq,
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dev->deliver_netinfo ||
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kthread_should_stop());
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if (dev->deliver_netinfo) {
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dev->deliver_netinfo--;
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if (dev->on_netinfo) {
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dev->on_netinfo(&dev->most_iface,
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dev->link_state,
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dev->mac_addrs);
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}
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}
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}
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return 0;
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}
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/**
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* retrieve_netinfo - retrieve network status from received buffer
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* @dev: private data
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* @mbo: received MBO
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*
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* Parse the message in buffer and get node address, link state, MAC address.
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* Wake up a thread to deliver this status to mostcore
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*/
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static void retrieve_netinfo(struct dim2_hdm *dev, struct mbo *mbo)
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{
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u8 *data = mbo->virt_address;
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pr_info("Node Address: 0x%03x\n", (u16)data[16] << 8 | data[17]);
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dev->link_state = data[18];
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pr_info("NIState: %d\n", dev->link_state);
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memcpy(dev->mac_addrs, data + 19, 6);
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dev->deliver_netinfo++;
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wake_up_interruptible(&dev->netinfo_waitq);
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}
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/**
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* service_done_flag - handle completed buffers
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* @dev: private data
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* @ch_idx: channel index
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*
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* Return back the completed buffers to mostcore, using completion callback
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*/
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static void service_done_flag(struct dim2_hdm *dev, int ch_idx)
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{
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struct hdm_channel *hdm_ch = dev->hch + ch_idx;
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struct dim_ch_state_t st;
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struct list_head *head;
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struct mbo *mbo;
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int done_buffers;
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unsigned long flags;
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u8 *data;
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BUG_ON(!hdm_ch);
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BUG_ON(!hdm_ch->is_initialized);
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spin_lock_irqsave(&dim_lock, flags);
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done_buffers = dim_get_channel_state(&hdm_ch->ch, &st)->done_buffers;
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if (!done_buffers) {
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spin_unlock_irqrestore(&dim_lock, flags);
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return;
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}
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if (!dim_detach_buffers(&hdm_ch->ch, done_buffers)) {
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spin_unlock_irqrestore(&dim_lock, flags);
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return;
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}
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spin_unlock_irqrestore(&dim_lock, flags);
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head = &hdm_ch->started_list;
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while (done_buffers) {
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spin_lock_irqsave(&dim_lock, flags);
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if (list_empty(head)) {
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spin_unlock_irqrestore(&dim_lock, flags);
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pr_crit("hard error: started_mbo list is empty whereas DIM2 has sent buffers\n");
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break;
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}
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mbo = list_first_entry(head, struct mbo, list);
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list_del(head->next);
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spin_unlock_irqrestore(&dim_lock, flags);
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data = mbo->virt_address;
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if (hdm_ch->data_type == MOST_CH_ASYNC &&
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hdm_ch->direction == MOST_CH_RX &&
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PACKET_IS_NET_INFO(data)) {
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retrieve_netinfo(dev, mbo);
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spin_lock_irqsave(&dim_lock, flags);
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list_add_tail(&mbo->list, &hdm_ch->pending_list);
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spin_unlock_irqrestore(&dim_lock, flags);
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} else {
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if (hdm_ch->data_type == MOST_CH_CONTROL ||
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hdm_ch->data_type == MOST_CH_ASYNC) {
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u32 const data_size =
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(u32)data[0] * 256 + data[1] + 2;
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mbo->processed_length =
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min_t(u32, data_size,
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mbo->buffer_length);
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} else {
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mbo->processed_length = mbo->buffer_length;
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}
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mbo->status = MBO_SUCCESS;
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mbo->complete(mbo);
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}
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done_buffers--;
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}
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}
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static struct dim_channel **get_active_channels(struct dim2_hdm *dev,
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struct dim_channel **buffer)
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{
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int idx = 0;
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int ch_idx;
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for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
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if (dev->hch[ch_idx].is_initialized)
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buffer[idx++] = &dev->hch[ch_idx].ch;
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}
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buffer[idx++] = NULL;
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return buffer;
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}
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static irqreturn_t dim2_mlb_isr(int irq, void *_dev)
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{
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struct dim2_hdm *dev = _dev;
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unsigned long flags;
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spin_lock_irqsave(&dim_lock, flags);
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dim_service_mlb_int_irq();
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spin_unlock_irqrestore(&dim_lock, flags);
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if (dev->atx_idx >= 0 && dev->hch[dev->atx_idx].is_initialized)
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while (!try_start_dim_transfer(dev->hch + dev->atx_idx))
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continue;
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return IRQ_HANDLED;
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}
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/**
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* dim2_tasklet_fn - tasklet function
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* @data: private data
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*
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* Service each initialized channel, if needed
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*/
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static void dim2_tasklet_fn(unsigned long data)
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{
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struct dim2_hdm *dev = (struct dim2_hdm *)data;
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unsigned long flags;
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int ch_idx;
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for (ch_idx = 0; ch_idx < DMA_CHANNELS; ch_idx++) {
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if (!dev->hch[ch_idx].is_initialized)
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continue;
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spin_lock_irqsave(&dim_lock, flags);
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dim_service_channel(&dev->hch[ch_idx].ch);
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spin_unlock_irqrestore(&dim_lock, flags);
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service_done_flag(dev, ch_idx);
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while (!try_start_dim_transfer(dev->hch + ch_idx))
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continue;
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}
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}
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/**
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* dim2_ahb_isr - interrupt service routine
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* @irq: irq number
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* @_dev: private data
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*
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* Acknowledge the interrupt and schedule a tasklet to service channels.
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* Return IRQ_HANDLED.
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*/
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static irqreturn_t dim2_ahb_isr(int irq, void *_dev)
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{
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struct dim2_hdm *dev = _dev;
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struct dim_channel *buffer[DMA_CHANNELS + 1];
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unsigned long flags;
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spin_lock_irqsave(&dim_lock, flags);
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dim_service_ahb_int_irq(get_active_channels(dev, buffer));
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spin_unlock_irqrestore(&dim_lock, flags);
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dim2_tasklet.data = (unsigned long)dev;
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tasklet_schedule(&dim2_tasklet);
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return IRQ_HANDLED;
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}
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/**
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* complete_all_mbos - complete MBO's in a list
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* @head: list head
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*
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* Delete all the entries in list and return back MBO's to mostcore using
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* completion call back.
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*/
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static void complete_all_mbos(struct list_head *head)
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{
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unsigned long flags;
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struct mbo *mbo;
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for (;;) {
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spin_lock_irqsave(&dim_lock, flags);
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if (list_empty(head)) {
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spin_unlock_irqrestore(&dim_lock, flags);
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break;
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}
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mbo = list_first_entry(head, struct mbo, list);
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list_del(head->next);
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spin_unlock_irqrestore(&dim_lock, flags);
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mbo->processed_length = 0;
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mbo->status = MBO_E_CLOSE;
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mbo->complete(mbo);
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}
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}
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/**
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* configure_channel - initialize a channel
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* @iface: interface the channel belongs to
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* @channel: channel to be configured
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* @channel_config: structure that holds the configuration information
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*
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* Receives configuration information from mostcore and initialize
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* the corresponding channel. Return 0 on success, negative on failure.
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*/
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static int configure_channel(struct most_interface *most_iface, int ch_idx,
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struct most_channel_config *ccfg)
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{
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struct dim2_hdm *dev = iface_to_hdm(most_iface);
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bool const is_tx = ccfg->direction == MOST_CH_TX;
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u16 const sub_size = ccfg->subbuffer_size;
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u16 const buf_size = ccfg->buffer_size;
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u16 new_size;
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unsigned long flags;
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u8 hal_ret;
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int const ch_addr = ch_idx * 2 + 2;
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struct hdm_channel *const hdm_ch = dev->hch + ch_idx;
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BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
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if (hdm_ch->is_initialized)
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return -EPERM;
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/* do not reset if the property was set by user, see poison_channel */
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hdm_ch->reset_dbr_size = ccfg->dbr_size ? NULL : &ccfg->dbr_size;
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/* zero value is default dbr_size, see dim2 hal */
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hdm_ch->ch.dbr_size = ccfg->dbr_size;
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switch (ccfg->data_type) {
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case MOST_CH_CONTROL:
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new_size = dim_norm_ctrl_async_buffer_size(buf_size);
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if (new_size == 0) {
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pr_err("%s: too small buffer size\n", hdm_ch->name);
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return -EINVAL;
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}
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ccfg->buffer_size = new_size;
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if (new_size != buf_size)
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pr_warn("%s: fixed buffer size (%d -> %d)\n",
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hdm_ch->name, buf_size, new_size);
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spin_lock_irqsave(&dim_lock, flags);
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hal_ret = dim_init_control(&hdm_ch->ch, is_tx, ch_addr,
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is_tx ? new_size * 2 : new_size);
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break;
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case MOST_CH_ASYNC:
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new_size = dim_norm_ctrl_async_buffer_size(buf_size);
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if (new_size == 0) {
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pr_err("%s: too small buffer size\n", hdm_ch->name);
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return -EINVAL;
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}
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ccfg->buffer_size = new_size;
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if (new_size != buf_size)
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pr_warn("%s: fixed buffer size (%d -> %d)\n",
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hdm_ch->name, buf_size, new_size);
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spin_lock_irqsave(&dim_lock, flags);
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hal_ret = dim_init_async(&hdm_ch->ch, is_tx, ch_addr,
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is_tx ? new_size * 2 : new_size);
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break;
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case MOST_CH_ISOC:
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new_size = dim_norm_isoc_buffer_size(buf_size, sub_size);
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if (new_size == 0) {
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pr_err("%s: invalid sub-buffer size or too small buffer size\n",
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hdm_ch->name);
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return -EINVAL;
|
}
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ccfg->buffer_size = new_size;
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if (new_size != buf_size)
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pr_warn("%s: fixed buffer size (%d -> %d)\n",
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hdm_ch->name, buf_size, new_size);
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spin_lock_irqsave(&dim_lock, flags);
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hal_ret = dim_init_isoc(&hdm_ch->ch, is_tx, ch_addr, sub_size);
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break;
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case MOST_CH_SYNC:
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new_size = dim_norm_sync_buffer_size(buf_size, sub_size);
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if (new_size == 0) {
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pr_err("%s: invalid sub-buffer size or too small buffer size\n",
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hdm_ch->name);
|
return -EINVAL;
|
}
|
ccfg->buffer_size = new_size;
|
if (new_size != buf_size)
|
pr_warn("%s: fixed buffer size (%d -> %d)\n",
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hdm_ch->name, buf_size, new_size);
|
spin_lock_irqsave(&dim_lock, flags);
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hal_ret = dim_init_sync(&hdm_ch->ch, is_tx, ch_addr, sub_size);
|
break;
|
default:
|
pr_err("%s: configure failed, bad channel type: %d\n",
|
hdm_ch->name, ccfg->data_type);
|
return -EINVAL;
|
}
|
|
if (hal_ret != DIM_NO_ERROR) {
|
spin_unlock_irqrestore(&dim_lock, flags);
|
pr_err("%s: configure failed (%d), type: %d, is_tx: %d\n",
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hdm_ch->name, hal_ret, ccfg->data_type, (int)is_tx);
|
return -ENODEV;
|
}
|
|
hdm_ch->data_type = ccfg->data_type;
|
hdm_ch->direction = ccfg->direction;
|
hdm_ch->is_initialized = true;
|
|
if (hdm_ch->data_type == MOST_CH_ASYNC &&
|
hdm_ch->direction == MOST_CH_TX &&
|
dev->atx_idx < 0)
|
dev->atx_idx = ch_idx;
|
|
spin_unlock_irqrestore(&dim_lock, flags);
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ccfg->dbr_size = hdm_ch->ch.dbr_size;
|
|
return 0;
|
}
|
|
/**
|
* enqueue - enqueue a buffer for data transfer
|
* @iface: intended interface
|
* @channel: ID of the channel the buffer is intended for
|
* @mbo: pointer to the buffer object
|
*
|
* Push the buffer into pending_list and try to transfer one buffer from
|
* pending_list. Return 0 on success, negative on failure.
|
*/
|
static int enqueue(struct most_interface *most_iface, int ch_idx,
|
struct mbo *mbo)
|
{
|
struct dim2_hdm *dev = iface_to_hdm(most_iface);
|
struct hdm_channel *hdm_ch = dev->hch + ch_idx;
|
unsigned long flags;
|
|
BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
|
|
if (!hdm_ch->is_initialized)
|
return -EPERM;
|
|
if (mbo->bus_address == 0)
|
return -EFAULT;
|
|
spin_lock_irqsave(&dim_lock, flags);
|
list_add_tail(&mbo->list, &hdm_ch->pending_list);
|
spin_unlock_irqrestore(&dim_lock, flags);
|
|
(void)try_start_dim_transfer(hdm_ch);
|
|
return 0;
|
}
|
|
/**
|
* request_netinfo - triggers retrieving of network info
|
* @iface: pointer to the interface
|
* @channel_id: corresponding channel ID
|
*
|
* Send a command to INIC which triggers retrieving of network info by means of
|
* "Message exchange over MDP/MEP". Return 0 on success, negative on failure.
|
*/
|
static void request_netinfo(struct most_interface *most_iface, int ch_idx,
|
void (*on_netinfo)(struct most_interface *,
|
unsigned char, unsigned char *))
|
{
|
struct dim2_hdm *dev = iface_to_hdm(most_iface);
|
struct mbo *mbo;
|
u8 *data;
|
|
dev->on_netinfo = on_netinfo;
|
if (!on_netinfo)
|
return;
|
|
if (dev->atx_idx < 0) {
|
pr_err("Async Tx Not initialized\n");
|
return;
|
}
|
|
mbo = most_get_mbo(&dev->most_iface, dev->atx_idx, NULL);
|
if (!mbo)
|
return;
|
|
mbo->buffer_length = 5;
|
|
data = mbo->virt_address;
|
|
data[0] = 0x00; /* PML High byte */
|
data[1] = 0x03; /* PML Low byte */
|
data[2] = 0x02; /* PMHL */
|
data[3] = 0x08; /* FPH */
|
data[4] = 0x40; /* FMF (FIFO cmd msg - Triggers NAOverMDP) */
|
|
most_submit_mbo(mbo);
|
}
|
|
/**
|
* poison_channel - poison buffers of a channel
|
* @iface: pointer to the interface the channel to be poisoned belongs to
|
* @channel_id: corresponding channel ID
|
*
|
* Destroy a channel and complete all the buffers in both started_list &
|
* pending_list. Return 0 on success, negative on failure.
|
*/
|
static int poison_channel(struct most_interface *most_iface, int ch_idx)
|
{
|
struct dim2_hdm *dev = iface_to_hdm(most_iface);
|
struct hdm_channel *hdm_ch = dev->hch + ch_idx;
|
unsigned long flags;
|
u8 hal_ret;
|
int ret = 0;
|
|
BUG_ON(ch_idx < 0 || ch_idx >= DMA_CHANNELS);
|
|
if (!hdm_ch->is_initialized)
|
return -EPERM;
|
|
tasklet_disable(&dim2_tasklet);
|
spin_lock_irqsave(&dim_lock, flags);
|
hal_ret = dim_destroy_channel(&hdm_ch->ch);
|
hdm_ch->is_initialized = false;
|
if (ch_idx == dev->atx_idx)
|
dev->atx_idx = -1;
|
spin_unlock_irqrestore(&dim_lock, flags);
|
tasklet_enable(&dim2_tasklet);
|
if (hal_ret != DIM_NO_ERROR) {
|
pr_err("HAL Failed to close channel %s\n", hdm_ch->name);
|
ret = -EFAULT;
|
}
|
|
complete_all_mbos(&hdm_ch->started_list);
|
complete_all_mbos(&hdm_ch->pending_list);
|
if (hdm_ch->reset_dbr_size)
|
*hdm_ch->reset_dbr_size = 0;
|
|
return ret;
|
}
|
|
static void *dma_alloc(struct mbo *mbo, u32 size)
|
{
|
struct device *dev = mbo->ifp->driver_dev;
|
|
return dma_alloc_coherent(dev, size, &mbo->bus_address, GFP_KERNEL);
|
}
|
|
static void dma_free(struct mbo *mbo, u32 size)
|
{
|
struct device *dev = mbo->ifp->driver_dev;
|
|
dma_free_coherent(dev, size, mbo->virt_address, mbo->bus_address);
|
}
|
|
static const struct of_device_id dim2_of_match[];
|
|
static struct {
|
const char *clock_speed;
|
u8 clk_speed;
|
} clk_mt[] = {
|
{ "256fs", CLK_256FS },
|
{ "512fs", CLK_512FS },
|
{ "1024fs", CLK_1024FS },
|
{ "2048fs", CLK_2048FS },
|
{ "3072fs", CLK_3072FS },
|
{ "4096fs", CLK_4096FS },
|
{ "6144fs", CLK_6144FS },
|
{ "8192fs", CLK_8192FS },
|
};
|
|
/**
|
* get_dim2_clk_speed - converts string to DIM2 clock speed value
|
*
|
* @clock_speed: string in the format "{NUMBER}fs"
|
* @val: pointer to get one of the CLK_{NUMBER}FS values
|
*
|
* By success stores one of the CLK_{NUMBER}FS in the *val and returns 0,
|
* otherwise returns -EINVAL.
|
*/
|
static int get_dim2_clk_speed(const char *clock_speed, u8 *val)
|
{
|
int i;
|
|
for (i = 0; i < ARRAY_SIZE(clk_mt); i++) {
|
if (!strcmp(clock_speed, clk_mt[i].clock_speed)) {
|
*val = clk_mt[i].clk_speed;
|
return 0;
|
}
|
}
|
return -EINVAL;
|
}
|
|
static void dim2_release(struct device *d)
|
{
|
struct dim2_hdm *dev = container_of(d, struct dim2_hdm, dev);
|
unsigned long flags;
|
|
kthread_stop(dev->netinfo_task);
|
|
spin_lock_irqsave(&dim_lock, flags);
|
dim_shutdown();
|
spin_unlock_irqrestore(&dim_lock, flags);
|
|
if (dev->disable_platform)
|
dev->disable_platform(to_platform_device(d->parent));
|
|
kfree(dev);
|
}
|
|
/*
|
* dim2_probe - dim2 probe handler
|
* @pdev: platform device structure
|
*
|
* Register the dim2 interface with mostcore and initialize it.
|
* Return 0 on success, negative on failure.
|
*/
|
static int dim2_probe(struct platform_device *pdev)
|
{
|
const struct dim2_platform_data *pdata;
|
const struct of_device_id *of_id;
|
const char *clock_speed;
|
struct dim2_hdm *dev;
|
struct resource *res;
|
int ret, i;
|
u8 hal_ret;
|
int irq;
|
|
enum { MLB_INT_IDX, AHB0_INT_IDX };
|
|
dev = kzalloc(sizeof(*dev), GFP_KERNEL);
|
if (!dev)
|
return -ENOMEM;
|
|
dev->atx_idx = -1;
|
|
platform_set_drvdata(pdev, dev);
|
|
ret = of_property_read_string(pdev->dev.of_node,
|
"microchip,clock-speed", &clock_speed);
|
if (ret) {
|
dev_err(&pdev->dev, "missing dt property clock-speed\n");
|
goto err_free_dev;
|
}
|
|
ret = get_dim2_clk_speed(clock_speed, &dev->clk_speed);
|
if (ret) {
|
dev_err(&pdev->dev, "bad dt property clock-speed\n");
|
goto err_free_dev;
|
}
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
dev->io_base = devm_ioremap_resource(&pdev->dev, res);
|
if (IS_ERR(dev->io_base)) {
|
ret = PTR_ERR(dev->io_base);
|
goto err_free_dev;
|
}
|
|
of_id = of_match_node(dim2_of_match, pdev->dev.of_node);
|
pdata = of_id->data;
|
ret = pdata && pdata->enable ? pdata->enable(pdev) : 0;
|
if (ret)
|
goto err_free_dev;
|
|
dev->disable_platform = pdata ? pdata->disable : NULL;
|
|
dev_info(&pdev->dev, "sync: num of frames per sub-buffer: %u\n", fcnt);
|
hal_ret = dim_startup(dev->io_base, dev->clk_speed, fcnt);
|
if (hal_ret != DIM_NO_ERROR) {
|
dev_err(&pdev->dev, "dim_startup failed: %d\n", hal_ret);
|
ret = -ENODEV;
|
goto err_disable_platform;
|
}
|
|
irq = platform_get_irq(pdev, AHB0_INT_IDX);
|
if (irq < 0) {
|
ret = irq;
|
goto err_shutdown_dim;
|
}
|
|
ret = devm_request_irq(&pdev->dev, irq, dim2_ahb_isr, 0,
|
"dim2_ahb0_int", dev);
|
if (ret) {
|
dev_err(&pdev->dev, "failed to request ahb0_int irq %d\n", irq);
|
goto err_shutdown_dim;
|
}
|
|
irq = platform_get_irq(pdev, MLB_INT_IDX);
|
if (irq < 0) {
|
ret = irq;
|
goto err_shutdown_dim;
|
}
|
|
ret = devm_request_irq(&pdev->dev, irq, dim2_mlb_isr, 0,
|
"dim2_mlb_int", dev);
|
if (ret) {
|
dev_err(&pdev->dev, "failed to request mlb_int irq %d\n", irq);
|
goto err_shutdown_dim;
|
}
|
|
init_waitqueue_head(&dev->netinfo_waitq);
|
dev->deliver_netinfo = 0;
|
dev->netinfo_task = kthread_run(&deliver_netinfo_thread, dev,
|
"dim2_netinfo");
|
if (IS_ERR(dev->netinfo_task)) {
|
ret = PTR_ERR(dev->netinfo_task);
|
goto err_shutdown_dim;
|
}
|
|
for (i = 0; i < DMA_CHANNELS; i++) {
|
struct most_channel_capability *cap = dev->capabilities + i;
|
struct hdm_channel *hdm_ch = dev->hch + i;
|
|
INIT_LIST_HEAD(&hdm_ch->pending_list);
|
INIT_LIST_HEAD(&hdm_ch->started_list);
|
hdm_ch->is_initialized = false;
|
snprintf(hdm_ch->name, sizeof(hdm_ch->name), "ca%d", i * 2 + 2);
|
|
cap->name_suffix = hdm_ch->name;
|
cap->direction = MOST_CH_RX | MOST_CH_TX;
|
cap->data_type = MOST_CH_CONTROL | MOST_CH_ASYNC |
|
MOST_CH_ISOC | MOST_CH_SYNC;
|
cap->num_buffers_packet = MAX_BUFFERS_PACKET;
|
cap->buffer_size_packet = MAX_BUF_SIZE_PACKET;
|
cap->num_buffers_streaming = MAX_BUFFERS_STREAMING;
|
cap->buffer_size_streaming = MAX_BUF_SIZE_STREAMING;
|
}
|
|
{
|
const char *fmt;
|
|
if (sizeof(res->start) == sizeof(long long))
|
fmt = "dim2-%016llx";
|
else if (sizeof(res->start) == sizeof(long))
|
fmt = "dim2-%016lx";
|
else
|
fmt = "dim2-%016x";
|
|
snprintf(dev->name, sizeof(dev->name), fmt, res->start);
|
}
|
|
dev->most_iface.interface = ITYPE_MEDIALB_DIM2;
|
dev->most_iface.description = dev->name;
|
dev->most_iface.num_channels = DMA_CHANNELS;
|
dev->most_iface.channel_vector = dev->capabilities;
|
dev->most_iface.configure = configure_channel;
|
dev->most_iface.enqueue = enqueue;
|
dev->most_iface.dma_alloc = dma_alloc;
|
dev->most_iface.dma_free = dma_free;
|
dev->most_iface.poison_channel = poison_channel;
|
dev->most_iface.request_netinfo = request_netinfo;
|
dev->most_iface.driver_dev = &pdev->dev;
|
dev->most_iface.dev = &dev->dev;
|
dev->dev.init_name = dev->name;
|
dev->dev.parent = &pdev->dev;
|
dev->dev.release = dim2_release;
|
|
return most_register_interface(&dev->most_iface);
|
|
err_shutdown_dim:
|
dim_shutdown();
|
err_disable_platform:
|
if (dev->disable_platform)
|
dev->disable_platform(pdev);
|
err_free_dev:
|
kfree(dev);
|
|
return ret;
|
}
|
|
/**
|
* dim2_remove - dim2 remove handler
|
* @pdev: platform device structure
|
*
|
* Unregister the interface from mostcore
|
*/
|
static int dim2_remove(struct platform_device *pdev)
|
{
|
struct dim2_hdm *dev = platform_get_drvdata(pdev);
|
|
most_deregister_interface(&dev->most_iface);
|
|
return 0;
|
}
|
|
/* platform specific functions [[ */
|
|
static int fsl_mx6_enable(struct platform_device *pdev)
|
{
|
struct dim2_hdm *dev = platform_get_drvdata(pdev);
|
int ret;
|
|
dev->clk = devm_clk_get(&pdev->dev, "mlb");
|
if (IS_ERR_OR_NULL(dev->clk)) {
|
dev_err(&pdev->dev, "unable to get mlb clock\n");
|
return -EFAULT;
|
}
|
|
ret = clk_prepare_enable(dev->clk);
|
if (ret) {
|
dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
|
return ret;
|
}
|
|
if (dev->clk_speed >= CLK_2048FS) {
|
/* enable pll */
|
dev->clk_pll = devm_clk_get(&pdev->dev, "pll8_mlb");
|
if (IS_ERR_OR_NULL(dev->clk_pll)) {
|
dev_err(&pdev->dev, "unable to get mlb pll clock\n");
|
clk_disable_unprepare(dev->clk);
|
return -EFAULT;
|
}
|
|
writel(0x888, dev->io_base + 0x38);
|
clk_prepare_enable(dev->clk_pll);
|
}
|
|
return 0;
|
}
|
|
static void fsl_mx6_disable(struct platform_device *pdev)
|
{
|
struct dim2_hdm *dev = platform_get_drvdata(pdev);
|
|
if (dev->clk_speed >= CLK_2048FS)
|
clk_disable_unprepare(dev->clk_pll);
|
|
clk_disable_unprepare(dev->clk);
|
}
|
|
static int rcar_h2_enable(struct platform_device *pdev)
|
{
|
struct dim2_hdm *dev = platform_get_drvdata(pdev);
|
int ret;
|
|
dev->clk = devm_clk_get(&pdev->dev, NULL);
|
if (IS_ERR(dev->clk)) {
|
dev_err(&pdev->dev, "cannot get clock\n");
|
return PTR_ERR(dev->clk);
|
}
|
|
ret = clk_prepare_enable(dev->clk);
|
if (ret) {
|
dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
|
return ret;
|
}
|
|
if (dev->clk_speed >= CLK_2048FS) {
|
/* enable MLP pll and LVDS drivers */
|
writel(0x03, dev->io_base + 0x600);
|
/* set bias */
|
writel(0x888, dev->io_base + 0x38);
|
} else {
|
/* PLL */
|
writel(0x04, dev->io_base + 0x600);
|
}
|
|
|
/* BBCR = 0b11 */
|
writel(0x03, dev->io_base + 0x500);
|
writel(0x0002FF02, dev->io_base + 0x508);
|
|
return 0;
|
}
|
|
static void rcar_h2_disable(struct platform_device *pdev)
|
{
|
struct dim2_hdm *dev = platform_get_drvdata(pdev);
|
|
clk_disable_unprepare(dev->clk);
|
|
/* disable PLLs and LVDS drivers */
|
writel(0x0, dev->io_base + 0x600);
|
}
|
|
static int rcar_m3_enable(struct platform_device *pdev)
|
{
|
struct dim2_hdm *dev = platform_get_drvdata(pdev);
|
u32 enable_512fs = dev->clk_speed == CLK_512FS;
|
int ret;
|
|
dev->clk = devm_clk_get(&pdev->dev, NULL);
|
if (IS_ERR(dev->clk)) {
|
dev_err(&pdev->dev, "cannot get clock\n");
|
return PTR_ERR(dev->clk);
|
}
|
|
ret = clk_prepare_enable(dev->clk);
|
if (ret) {
|
dev_err(&pdev->dev, "%s\n", "clk_prepare_enable failed");
|
return ret;
|
}
|
|
/* PLL */
|
writel(0x04, dev->io_base + 0x600);
|
|
writel(enable_512fs, dev->io_base + 0x604);
|
|
/* BBCR = 0b11 */
|
writel(0x03, dev->io_base + 0x500);
|
writel(0x0002FF02, dev->io_base + 0x508);
|
|
return 0;
|
}
|
|
static void rcar_m3_disable(struct platform_device *pdev)
|
{
|
struct dim2_hdm *dev = platform_get_drvdata(pdev);
|
|
clk_disable_unprepare(dev->clk);
|
|
/* disable PLLs and LVDS drivers */
|
writel(0x0, dev->io_base + 0x600);
|
}
|
|
/* ]] platform specific functions */
|
|
enum dim2_platforms { FSL_MX6, RCAR_H2, RCAR_M3 };
|
|
static struct dim2_platform_data plat_data[] = {
|
[FSL_MX6] = { .enable = fsl_mx6_enable, .disable = fsl_mx6_disable },
|
[RCAR_H2] = { .enable = rcar_h2_enable, .disable = rcar_h2_disable },
|
[RCAR_M3] = { .enable = rcar_m3_enable, .disable = rcar_m3_disable },
|
};
|
|
static const struct of_device_id dim2_of_match[] = {
|
{
|
.compatible = "fsl,imx6q-mlb150",
|
.data = plat_data + FSL_MX6
|
},
|
{
|
.compatible = "renesas,mlp",
|
.data = plat_data + RCAR_H2
|
},
|
{
|
.compatible = "rcar,medialb-dim2",
|
.data = plat_data + RCAR_M3
|
},
|
{
|
.compatible = "xlnx,axi4-os62420_3pin-1.00.a",
|
},
|
{
|
.compatible = "xlnx,axi4-os62420_6pin-1.00.a",
|
},
|
{},
|
};
|
|
MODULE_DEVICE_TABLE(of, dim2_of_match);
|
|
static struct platform_driver dim2_driver = {
|
.probe = dim2_probe,
|
.remove = dim2_remove,
|
.driver = {
|
.name = "hdm_dim2",
|
.of_match_table = dim2_of_match,
|
.dev_groups = dim2_groups,
|
},
|
};
|
|
module_platform_driver(dim2_driver);
|
|
MODULE_AUTHOR("Andrey Shvetsov <andrey.shvetsov@k2l.de>");
|
MODULE_DESCRIPTION("MediaLB DIM2 Hardware Dependent Module");
|
MODULE_LICENSE("GPL");
|
