/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com> */
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#ifndef _UAPI_TEGRA_VDE_H_
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#define _UAPI_TEGRA_VDE_H_
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#include <linux/types.h>
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#include <asm/ioctl.h>
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#define FLAG_B_FRAME 0x1
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#define FLAG_REFERENCE 0x2
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struct tegra_vde_h264_frame {
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__s32 y_fd;
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__s32 cb_fd;
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__s32 cr_fd;
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__s32 aux_fd;
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__u32 y_offset;
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__u32 cb_offset;
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__u32 cr_offset;
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__u32 aux_offset;
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__u32 frame_num;
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__u32 flags;
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// Must be zero'ed
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__u32 reserved[6];
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};
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struct tegra_vde_h264_decoder_ctx {
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__s32 bitstream_data_fd;
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__u32 bitstream_data_offset;
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__u64 dpb_frames_ptr;
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__u32 dpb_frames_nb;
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__u32 dpb_ref_frames_with_earlier_poc_nb;
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// SPS
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__u32 baseline_profile;
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__u32 level_idc;
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__u32 log2_max_pic_order_cnt_lsb;
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__u32 log2_max_frame_num;
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__u32 pic_order_cnt_type;
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__u32 direct_8x8_inference_flag;
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__u32 pic_width_in_mbs;
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__u32 pic_height_in_mbs;
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// PPS
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__u32 pic_init_qp;
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__u32 deblocking_filter_control_present_flag;
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__u32 constrained_intra_pred_flag;
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__u32 chroma_qp_index_offset;
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__u32 pic_order_present_flag;
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// Slice header
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__u32 num_ref_idx_l0_active_minus1;
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__u32 num_ref_idx_l1_active_minus1;
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// Must be zero'ed
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__u32 reserved[11];
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};
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#define VDE_IOCTL_BASE ('v' + 0x20)
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#define VDE_IO(nr) _IO(VDE_IOCTL_BASE, nr)
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#define VDE_IOR(nr, type) _IOR(VDE_IOCTL_BASE, nr, type)
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#define VDE_IOW(nr, type) _IOW(VDE_IOCTL_BASE, nr, type)
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#define VDE_IOWR(nr, type) _IOWR(VDE_IOCTL_BASE, nr, type)
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#define TEGRA_VDE_DECODE_H264 0x00
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#define TEGRA_VDE_IOCTL_DECODE_H264 \
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VDE_IOW(TEGRA_VDE_DECODE_H264, struct tegra_vde_h264_decoder_ctx)
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#endif // _UAPI_TEGRA_VDE_H_
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