/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Cedrus VPU driver
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*
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* Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com>
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* Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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* Copyright (C) 2018 Bootlin
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*
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* Based on the vim2m driver, that is:
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*
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* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
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* Pawel Osciak, <pawel@osciak.com>
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* Marek Szyprowski, <m.szyprowski@samsung.com>
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*/
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#ifndef _CEDRUS_H_
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#define _CEDRUS_H_
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-mem2mem.h>
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#include <media/videobuf2-v4l2.h>
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#include <media/videobuf2-dma-contig.h>
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#include <linux/platform_device.h>
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#define CEDRUS_NAME "cedrus"
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#define CEDRUS_CAPABILITY_UNTILED BIT(0)
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#define CEDRUS_CAPABILITY_H265_DEC BIT(1)
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#define CEDRUS_QUIRK_NO_DMA_OFFSET BIT(0)
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enum cedrus_codec {
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CEDRUS_CODEC_MPEG2,
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CEDRUS_CODEC_H264,
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CEDRUS_CODEC_H265,
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CEDRUS_CODEC_LAST,
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};
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enum cedrus_irq_status {
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CEDRUS_IRQ_NONE,
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CEDRUS_IRQ_ERROR,
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CEDRUS_IRQ_OK,
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};
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enum cedrus_h264_pic_type {
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CEDRUS_H264_PIC_TYPE_FRAME = 0,
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CEDRUS_H264_PIC_TYPE_FIELD,
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CEDRUS_H264_PIC_TYPE_MBAFF,
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};
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struct cedrus_control {
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struct v4l2_ctrl_config cfg;
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enum cedrus_codec codec;
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unsigned char required:1;
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};
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struct cedrus_h264_run {
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const struct v4l2_ctrl_h264_decode_params *decode_params;
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const struct v4l2_ctrl_h264_pps *pps;
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const struct v4l2_ctrl_h264_scaling_matrix *scaling_matrix;
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const struct v4l2_ctrl_h264_slice_params *slice_params;
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const struct v4l2_ctrl_h264_sps *sps;
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const struct v4l2_ctrl_h264_pred_weights *pred_weights;
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};
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struct cedrus_mpeg2_run {
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const struct v4l2_ctrl_mpeg2_slice_params *slice_params;
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const struct v4l2_ctrl_mpeg2_quantization *quantization;
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};
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struct cedrus_h265_run {
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const struct v4l2_ctrl_hevc_sps *sps;
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const struct v4l2_ctrl_hevc_pps *pps;
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const struct v4l2_ctrl_hevc_slice_params *slice_params;
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};
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struct cedrus_run {
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struct vb2_v4l2_buffer *src;
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struct vb2_v4l2_buffer *dst;
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union {
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struct cedrus_h264_run h264;
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struct cedrus_mpeg2_run mpeg2;
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struct cedrus_h265_run h265;
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};
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};
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struct cedrus_buffer {
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struct v4l2_m2m_buffer m2m_buf;
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union {
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struct {
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unsigned int position;
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enum cedrus_h264_pic_type pic_type;
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} h264;
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} codec;
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};
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struct cedrus_ctx {
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struct v4l2_fh fh;
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struct cedrus_dev *dev;
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struct v4l2_pix_format src_fmt;
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struct v4l2_pix_format dst_fmt;
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enum cedrus_codec current_codec;
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struct v4l2_ctrl_handler hdl;
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struct v4l2_ctrl **ctrls;
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union {
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struct {
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void *mv_col_buf;
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dma_addr_t mv_col_buf_dma;
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ssize_t mv_col_buf_field_size;
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ssize_t mv_col_buf_size;
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void *pic_info_buf;
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dma_addr_t pic_info_buf_dma;
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ssize_t pic_info_buf_size;
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void *neighbor_info_buf;
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dma_addr_t neighbor_info_buf_dma;
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void *deblk_buf;
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dma_addr_t deblk_buf_dma;
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ssize_t deblk_buf_size;
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void *intra_pred_buf;
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dma_addr_t intra_pred_buf_dma;
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ssize_t intra_pred_buf_size;
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} h264;
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struct {
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void *mv_col_buf;
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dma_addr_t mv_col_buf_addr;
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ssize_t mv_col_buf_size;
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ssize_t mv_col_buf_unit_size;
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void *neighbor_info_buf;
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dma_addr_t neighbor_info_buf_addr;
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} h265;
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} codec;
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};
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struct cedrus_dec_ops {
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void (*irq_clear)(struct cedrus_ctx *ctx);
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void (*irq_disable)(struct cedrus_ctx *ctx);
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enum cedrus_irq_status (*irq_status)(struct cedrus_ctx *ctx);
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void (*setup)(struct cedrus_ctx *ctx, struct cedrus_run *run);
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int (*start)(struct cedrus_ctx *ctx);
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void (*stop)(struct cedrus_ctx *ctx);
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void (*trigger)(struct cedrus_ctx *ctx);
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};
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struct cedrus_variant {
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unsigned int capabilities;
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unsigned int quirks;
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unsigned int mod_rate;
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};
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struct cedrus_dev {
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struct v4l2_device v4l2_dev;
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struct video_device vfd;
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struct media_device mdev;
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struct media_pad pad[2];
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struct platform_device *pdev;
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struct device *dev;
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struct v4l2_m2m_dev *m2m_dev;
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struct cedrus_dec_ops *dec_ops[CEDRUS_CODEC_LAST];
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/* Device file mutex */
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struct mutex dev_mutex;
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void __iomem *base;
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struct clk *mod_clk;
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struct clk *ahb_clk;
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struct clk *ram_clk;
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struct reset_control *rstc;
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unsigned int capabilities;
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};
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extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2;
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extern struct cedrus_dec_ops cedrus_dec_ops_h264;
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extern struct cedrus_dec_ops cedrus_dec_ops_h265;
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static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val)
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{
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writel(val, dev->base + reg);
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}
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static inline u32 cedrus_read(struct cedrus_dev *dev, u32 reg)
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{
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return readl(dev->base + reg);
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}
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static inline dma_addr_t cedrus_buf_addr(struct vb2_buffer *buf,
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struct v4l2_pix_format *pix_fmt,
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unsigned int plane)
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{
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dma_addr_t addr = vb2_dma_contig_plane_dma_addr(buf, 0);
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return addr + (pix_fmt ? (dma_addr_t)pix_fmt->bytesperline *
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pix_fmt->height * plane : 0);
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}
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static inline dma_addr_t cedrus_dst_buf_addr(struct cedrus_ctx *ctx,
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int index, unsigned int plane)
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{
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struct vb2_buffer *buf = NULL;
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struct vb2_queue *vq;
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if (index < 0)
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return 0;
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vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
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if (vq)
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buf = vb2_get_buffer(vq, index);
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return buf ? cedrus_buf_addr(buf, &ctx->dst_fmt, plane) : 0;
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}
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static inline struct cedrus_buffer *
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vb2_v4l2_to_cedrus_buffer(const struct vb2_v4l2_buffer *p)
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{
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return container_of(p, struct cedrus_buffer, m2m_buf.vb);
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}
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static inline struct cedrus_buffer *
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vb2_to_cedrus_buffer(const struct vb2_buffer *p)
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{
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return vb2_v4l2_to_cedrus_buffer(to_vb2_v4l2_buffer(p));
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}
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void *cedrus_find_control_data(struct cedrus_ctx *ctx, u32 id);
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#endif
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