// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Maxime Jourdan <maxi.jourdan@wanadoo.fr>
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*
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* VDEC_HEVC is a video decoding block that allows decoding of
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* HEVC, VP9
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*/
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#include <linux/firmware.h>
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#include <linux/clk.h>
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#include "vdec_1.h"
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#include "vdec_helpers.h"
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#include "vdec_hevc.h"
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#include "hevc_regs.h"
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#include "dos_regs.h"
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/* AO Registers */
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#define AO_RTI_GEN_PWR_SLEEP0 0xe8
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#define AO_RTI_GEN_PWR_ISO0 0xec
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#define GEN_PWR_VDEC_HEVC (BIT(7) | BIT(6))
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#define GEN_PWR_VDEC_HEVC_SM1 (BIT(2))
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#define MC_SIZE (4096 * 4)
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static int vdec_hevc_load_firmware(struct amvdec_session *sess,
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const char *fwname)
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{
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struct amvdec_core *core = sess->core;
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struct device *dev = core->dev_dec;
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const struct firmware *fw;
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static void *mc_addr;
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static dma_addr_t mc_addr_map;
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int ret;
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u32 i = 100;
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ret = request_firmware(&fw, fwname, dev);
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if (ret < 0) {
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dev_err(dev, "Unable to request firmware %s\n", fwname);
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return ret;
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}
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if (fw->size < MC_SIZE) {
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dev_err(dev, "Firmware size %zu is too small. Expected %u.\n",
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fw->size, MC_SIZE);
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ret = -EINVAL;
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goto release_firmware;
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}
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mc_addr = dma_alloc_coherent(core->dev, MC_SIZE, &mc_addr_map,
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GFP_KERNEL);
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if (!mc_addr) {
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ret = -ENOMEM;
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goto release_firmware;
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}
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memcpy(mc_addr, fw->data, MC_SIZE);
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amvdec_write_dos(core, HEVC_MPSR, 0);
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amvdec_write_dos(core, HEVC_CPSR, 0);
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amvdec_write_dos(core, HEVC_IMEM_DMA_ADR, mc_addr_map);
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amvdec_write_dos(core, HEVC_IMEM_DMA_COUNT, MC_SIZE / 4);
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amvdec_write_dos(core, HEVC_IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
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while (i && (readl(core->dos_base + HEVC_IMEM_DMA_CTRL) & 0x8000))
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i--;
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if (i == 0) {
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dev_err(dev, "Firmware load fail (DMA hang?)\n");
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ret = -ENODEV;
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}
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dma_free_coherent(core->dev, MC_SIZE, mc_addr, mc_addr_map);
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release_firmware:
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release_firmware(fw);
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return ret;
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}
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static void vdec_hevc_stbuf_init(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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amvdec_write_dos(core, HEVC_STREAM_CONTROL,
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amvdec_read_dos(core, HEVC_STREAM_CONTROL) & ~1);
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amvdec_write_dos(core, HEVC_STREAM_START_ADDR, sess->vififo_paddr);
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amvdec_write_dos(core, HEVC_STREAM_END_ADDR,
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sess->vififo_paddr + sess->vififo_size);
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amvdec_write_dos(core, HEVC_STREAM_RD_PTR, sess->vififo_paddr);
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amvdec_write_dos(core, HEVC_STREAM_WR_PTR, sess->vififo_paddr);
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}
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/* VDEC_HEVC specific ESPARSER configuration */
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static void vdec_hevc_conf_esparser(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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/* set vififo_vbuf_rp_sel=>vdec_hevc */
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amvdec_write_dos(core, DOS_GEN_CTRL0, 3 << 1);
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amvdec_write_dos(core, HEVC_STREAM_CONTROL,
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amvdec_read_dos(core, HEVC_STREAM_CONTROL) | BIT(3));
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amvdec_write_dos(core, HEVC_STREAM_CONTROL,
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amvdec_read_dos(core, HEVC_STREAM_CONTROL) | 1);
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amvdec_write_dos(core, HEVC_STREAM_FIFO_CTL,
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amvdec_read_dos(core, HEVC_STREAM_FIFO_CTL) | BIT(29));
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}
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static u32 vdec_hevc_vififo_level(struct amvdec_session *sess)
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{
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return readl_relaxed(sess->core->dos_base + HEVC_STREAM_LEVEL);
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}
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static int vdec_hevc_stop(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
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/* Disable interrupt */
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amvdec_write_dos(core, HEVC_ASSIST_MBOX1_MASK, 0);
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/* Disable firmware processor */
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amvdec_write_dos(core, HEVC_MPSR, 0);
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if (sess->priv)
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codec_ops->stop(sess);
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/* Enable VDEC_HEVC Isolation */
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if (core->platform->revision == VDEC_REVISION_SM1)
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
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GEN_PWR_VDEC_HEVC_SM1,
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GEN_PWR_VDEC_HEVC_SM1);
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else
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
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0xc00, 0xc00);
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/* VDEC_HEVC Memories */
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amvdec_write_dos(core, DOS_MEM_PD_HEVC, 0xffffffffUL);
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if (core->platform->revision == VDEC_REVISION_SM1)
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VDEC_HEVC_SM1,
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GEN_PWR_VDEC_HEVC_SM1);
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else
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VDEC_HEVC, GEN_PWR_VDEC_HEVC);
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clk_disable_unprepare(core->vdec_hevc_clk);
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if (core->platform->revision == VDEC_REVISION_G12A ||
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core->platform->revision == VDEC_REVISION_SM1)
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clk_disable_unprepare(core->vdec_hevcf_clk);
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return 0;
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}
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static int vdec_hevc_start(struct amvdec_session *sess)
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{
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int ret;
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struct amvdec_core *core = sess->core;
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struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
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if (core->platform->revision == VDEC_REVISION_G12A ||
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core->platform->revision == VDEC_REVISION_SM1) {
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clk_set_rate(core->vdec_hevcf_clk, 666666666);
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ret = clk_prepare_enable(core->vdec_hevcf_clk);
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if (ret)
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return ret;
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}
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clk_set_rate(core->vdec_hevc_clk, 666666666);
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ret = clk_prepare_enable(core->vdec_hevc_clk);
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if (ret) {
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if (core->platform->revision == VDEC_REVISION_G12A ||
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core->platform->revision == VDEC_REVISION_SM1)
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clk_disable_unprepare(core->vdec_hevcf_clk);
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return ret;
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}
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if (core->platform->revision == VDEC_REVISION_SM1)
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VDEC_HEVC_SM1, 0);
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else
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VDEC_HEVC, 0);
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usleep_range(10, 20);
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/* Reset VDEC_HEVC*/
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amvdec_write_dos(core, DOS_SW_RESET3, 0xffffffff);
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amvdec_write_dos(core, DOS_SW_RESET3, 0x00000000);
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amvdec_write_dos(core, DOS_GCLK_EN3, 0xffffffff);
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/* VDEC_HEVC Memories */
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amvdec_write_dos(core, DOS_MEM_PD_HEVC, 0x00000000);
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/* Remove VDEC_HEVC Isolation */
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if (core->platform->revision == VDEC_REVISION_SM1)
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
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GEN_PWR_VDEC_HEVC_SM1, 0);
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else
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
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0xc00, 0);
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amvdec_write_dos(core, DOS_SW_RESET3, 0xffffffff);
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amvdec_write_dos(core, DOS_SW_RESET3, 0x00000000);
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vdec_hevc_stbuf_init(sess);
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ret = vdec_hevc_load_firmware(sess, sess->fmt_out->firmware_path);
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if (ret)
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goto stop;
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ret = codec_ops->start(sess);
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if (ret)
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goto stop;
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amvdec_write_dos(core, DOS_SW_RESET3, BIT(12) | BIT(11));
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amvdec_write_dos(core, DOS_SW_RESET3, 0);
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amvdec_read_dos(core, DOS_SW_RESET3);
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amvdec_write_dos(core, HEVC_MPSR, 1);
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/* Let the firmware settle */
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usleep_range(10, 20);
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return 0;
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stop:
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vdec_hevc_stop(sess);
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return ret;
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}
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struct amvdec_ops vdec_hevc_ops = {
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.start = vdec_hevc_start,
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.stop = vdec_hevc_stop,
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.conf_esparser = vdec_hevc_conf_esparser,
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.vififo_level = vdec_hevc_vififo_level,
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};
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