// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Maxime Jourdan <mjourdan@baylibre.com>
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*
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* VDEC_1 is a video decoding block that allows decoding of
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* MPEG 1/2/4, H.263, H.264, MJPEG, VC1
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*/
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#include <linux/firmware.h>
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#include <linux/clk.h>
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#include "vdec_1.h"
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#include "vdec_helpers.h"
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#include "dos_regs.h"
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/* AO Registers */
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#define AO_RTI_GEN_PWR_SLEEP0 0xe8
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#define AO_RTI_GEN_PWR_ISO0 0xec
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#define GEN_PWR_VDEC_1 (BIT(3) | BIT(2))
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#define GEN_PWR_VDEC_1_SM1 (BIT(1))
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#define MC_SIZE (4096 * 4)
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static int
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vdec_1_load_firmware(struct amvdec_session *sess, const char *fwname)
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{
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const struct firmware *fw;
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struct amvdec_core *core = sess->core;
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struct device *dev = core->dev_dec;
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struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
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static void *mc_addr;
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static dma_addr_t mc_addr_map;
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int ret;
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u32 i = 1000;
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ret = request_firmware(&fw, fwname, dev);
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if (ret < 0)
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return -EINVAL;
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if (fw->size < MC_SIZE) {
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dev_err(dev, "Firmware size %zu is too small. Expected %u.\n",
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fw->size, MC_SIZE);
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ret = -EINVAL;
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goto release_firmware;
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}
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mc_addr = dma_alloc_coherent(core->dev, MC_SIZE,
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&mc_addr_map, GFP_KERNEL);
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if (!mc_addr) {
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ret = -ENOMEM;
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goto release_firmware;
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}
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memcpy(mc_addr, fw->data, MC_SIZE);
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amvdec_write_dos(core, MPSR, 0);
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amvdec_write_dos(core, CPSR, 0);
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amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31));
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amvdec_write_dos(core, IMEM_DMA_ADR, mc_addr_map);
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amvdec_write_dos(core, IMEM_DMA_COUNT, MC_SIZE / 4);
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amvdec_write_dos(core, IMEM_DMA_CTRL, (0x8000 | (7 << 16)));
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while (--i && amvdec_read_dos(core, IMEM_DMA_CTRL) & 0x8000);
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if (i == 0) {
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dev_err(dev, "Firmware load fail (DMA hang?)\n");
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ret = -EINVAL;
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goto free_mc;
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}
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if (codec_ops->load_extended_firmware)
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ret = codec_ops->load_extended_firmware(sess,
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fw->data + MC_SIZE,
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fw->size - MC_SIZE);
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free_mc:
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dma_free_coherent(core->dev, MC_SIZE, mc_addr, mc_addr_map);
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release_firmware:
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release_firmware(fw);
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return ret;
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}
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static int vdec_1_stbuf_power_up(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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amvdec_write_dos(core, VLD_MEM_VIFIFO_CONTROL, 0);
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amvdec_write_dos(core, VLD_MEM_VIFIFO_WRAP_COUNT, 0);
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amvdec_write_dos(core, POWER_CTL_VLD, BIT(4));
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amvdec_write_dos(core, VLD_MEM_VIFIFO_START_PTR, sess->vififo_paddr);
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amvdec_write_dos(core, VLD_MEM_VIFIFO_CURR_PTR, sess->vififo_paddr);
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amvdec_write_dos(core, VLD_MEM_VIFIFO_END_PTR,
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sess->vififo_paddr + sess->vififo_size - 8);
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amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_CONTROL, 1);
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amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_CONTROL, 1);
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amvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, MEM_BUFCTRL_MANUAL);
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amvdec_write_dos(core, VLD_MEM_VIFIFO_WP, sess->vififo_paddr);
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amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
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amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
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amvdec_write_dos_bits(core, VLD_MEM_VIFIFO_CONTROL,
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(0x11 << MEM_FIFO_CNT_BIT) | MEM_FILL_ON_LEVEL |
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MEM_CTRL_FILL_EN | MEM_CTRL_EMPTY_EN);
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return 0;
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}
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static void vdec_1_conf_esparser(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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/* VDEC_1 specific ESPARSER stuff */
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amvdec_write_dos(core, DOS_GEN_CTRL0, 0);
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amvdec_write_dos(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
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amvdec_clear_dos_bits(core, VLD_MEM_VIFIFO_BUF_CNTL, 1);
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}
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static u32 vdec_1_vififo_level(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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return amvdec_read_dos(core, VLD_MEM_VIFIFO_LEVEL);
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}
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static int vdec_1_stop(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
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amvdec_write_dos(core, MPSR, 0);
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amvdec_write_dos(core, CPSR, 0);
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amvdec_write_dos(core, ASSIST_MBOX1_MASK, 0);
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amvdec_write_dos(core, DOS_SW_RESET0, BIT(12) | BIT(11));
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amvdec_write_dos(core, DOS_SW_RESET0, 0);
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amvdec_read_dos(core, DOS_SW_RESET0);
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/* enable vdec1 isolation */
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if (core->platform->revision == VDEC_REVISION_SM1)
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
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GEN_PWR_VDEC_1_SM1, GEN_PWR_VDEC_1_SM1);
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else
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regmap_write(core->regmap_ao, AO_RTI_GEN_PWR_ISO0, 0xc0);
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/* power off vdec1 memories */
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amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0xffffffff);
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/* power off vdec1 */
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if (core->platform->revision == VDEC_REVISION_SM1)
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VDEC_1_SM1, GEN_PWR_VDEC_1_SM1);
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else
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VDEC_1, GEN_PWR_VDEC_1);
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clk_disable_unprepare(core->vdec_1_clk);
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if (sess->priv)
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codec_ops->stop(sess);
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return 0;
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}
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static int vdec_1_start(struct amvdec_session *sess)
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{
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int ret;
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struct amvdec_core *core = sess->core;
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struct amvdec_codec_ops *codec_ops = sess->fmt_out->codec_ops;
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/* Configure the vdec clk to the maximum available */
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clk_set_rate(core->vdec_1_clk, 666666666);
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ret = clk_prepare_enable(core->vdec_1_clk);
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if (ret)
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return ret;
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/* Enable power for VDEC_1 */
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if (core->platform->revision == VDEC_REVISION_SM1)
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VDEC_1_SM1, 0);
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else
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VDEC_1, 0);
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usleep_range(10, 20);
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/* Reset VDEC1 */
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amvdec_write_dos(core, DOS_SW_RESET0, 0xfffffffc);
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amvdec_write_dos(core, DOS_SW_RESET0, 0x00000000);
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amvdec_write_dos(core, DOS_GCLK_EN0, 0x3ff);
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/* enable VDEC Memories */
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amvdec_write_dos(core, DOS_MEM_PD_VDEC, 0);
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/* Remove VDEC1 Isolation */
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if (core->platform->revision == VDEC_REVISION_SM1)
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regmap_update_bits(core->regmap_ao, AO_RTI_GEN_PWR_ISO0,
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GEN_PWR_VDEC_1_SM1, 0);
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else
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regmap_write(core->regmap_ao, AO_RTI_GEN_PWR_ISO0, 0);
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/* Reset DOS top registers */
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amvdec_write_dos(core, DOS_VDEC_MCRCC_STALL_CTRL, 0);
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amvdec_write_dos(core, GCLK_EN, 0x3ff);
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amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(31));
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vdec_1_stbuf_power_up(sess);
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ret = vdec_1_load_firmware(sess, sess->fmt_out->firmware_path);
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if (ret)
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goto stop;
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ret = codec_ops->start(sess);
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if (ret)
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goto stop;
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/* Enable IRQ */
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amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
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amvdec_write_dos(core, ASSIST_MBOX1_MASK, 1);
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/* Enable 2-plane output */
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if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
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amvdec_write_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(17));
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else
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amvdec_clear_dos_bits(core, MDEC_PIC_DC_CTRL, BIT(17));
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/* Enable firmware processor */
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amvdec_write_dos(core, MPSR, 1);
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/* Let the firmware settle */
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usleep_range(10, 20);
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return 0;
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stop:
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vdec_1_stop(sess);
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return ret;
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}
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struct amvdec_ops vdec_1_ops = {
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.start = vdec_1_start,
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.stop = vdec_1_stop,
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.conf_esparser = vdec_1_conf_esparser,
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.vififo_level = vdec_1_vififo_level,
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};
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