// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 BayLibre, SAS
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* Author: Maxime Jourdan <mjourdan@baylibre.com>
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*/
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#include <media/v4l2-mem2mem.h>
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#include <media/videobuf2-dma-contig.h>
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#include "codec_mpeg12.h"
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#include "dos_regs.h"
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#include "vdec_helpers.h"
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#define SIZE_WORKSPACE SZ_128K
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/* Offset substracted by the firmware from the workspace paddr */
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#define WORKSPACE_OFFSET (5 * SZ_1K)
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/* map firmware registers to known MPEG1/2 functions */
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#define MREG_SEQ_INFO AV_SCRATCH_4
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#define MPEG2_SEQ_DAR_MASK GENMASK(3, 0)
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#define MPEG2_DAR_4_3 2
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#define MPEG2_DAR_16_9 3
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#define MPEG2_DAR_221_100 4
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#define MREG_PIC_INFO AV_SCRATCH_5
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#define MREG_PIC_WIDTH AV_SCRATCH_6
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#define MREG_PIC_HEIGHT AV_SCRATCH_7
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#define MREG_BUFFERIN AV_SCRATCH_8
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#define MREG_BUFFEROUT AV_SCRATCH_9
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#define MREG_CMD AV_SCRATCH_A
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#define MREG_CO_MV_START AV_SCRATCH_B
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#define MREG_ERROR_COUNT AV_SCRATCH_C
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#define MREG_FRAME_OFFSET AV_SCRATCH_D
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#define MREG_WAIT_BUFFER AV_SCRATCH_E
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#define MREG_FATAL_ERROR AV_SCRATCH_F
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#define PICINFO_PROG 0x00008000
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#define PICINFO_TOP_FIRST 0x00002000
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struct codec_mpeg12 {
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/* Buffer for the MPEG1/2 Workspace */
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void *workspace_vaddr;
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dma_addr_t workspace_paddr;
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};
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static const u8 eos_sequence[SZ_1K] = { 0x00, 0x00, 0x01, 0xB7 };
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static const u8 *codec_mpeg12_eos_sequence(u32 *len)
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{
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*len = ARRAY_SIZE(eos_sequence);
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return eos_sequence;
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}
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static int codec_mpeg12_can_recycle(struct amvdec_core *core)
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{
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return !amvdec_read_dos(core, MREG_BUFFERIN);
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}
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static void codec_mpeg12_recycle(struct amvdec_core *core, u32 buf_idx)
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{
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amvdec_write_dos(core, MREG_BUFFERIN, buf_idx + 1);
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}
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static int codec_mpeg12_start(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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struct codec_mpeg12 *mpeg12;
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int ret;
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mpeg12 = kzalloc(sizeof(*mpeg12), GFP_KERNEL);
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if (!mpeg12)
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return -ENOMEM;
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/* Allocate some memory for the MPEG1/2 decoder's state */
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mpeg12->workspace_vaddr = dma_alloc_coherent(core->dev, SIZE_WORKSPACE,
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&mpeg12->workspace_paddr,
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GFP_KERNEL);
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if (!mpeg12->workspace_vaddr) {
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dev_err(core->dev, "Failed to request MPEG 1/2 Workspace\n");
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ret = -ENOMEM;
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goto free_mpeg12;
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}
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ret = amvdec_set_canvases(sess, (u32[]){ AV_SCRATCH_0, 0 },
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(u32[]){ 8, 0 });
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if (ret)
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goto free_workspace;
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amvdec_write_dos(core, POWER_CTL_VLD, BIT(4));
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amvdec_write_dos(core, MREG_CO_MV_START,
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mpeg12->workspace_paddr + WORKSPACE_OFFSET);
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amvdec_write_dos(core, MPEG1_2_REG, 0);
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amvdec_write_dos(core, PSCALE_CTRL, 0);
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amvdec_write_dos(core, PIC_HEAD_INFO, 0x380);
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amvdec_write_dos(core, M4_CONTROL_REG, 0);
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amvdec_write_dos(core, MREG_BUFFERIN, 0);
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amvdec_write_dos(core, MREG_BUFFEROUT, 0);
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amvdec_write_dos(core, MREG_CMD, (sess->width << 16) | sess->height);
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amvdec_write_dos(core, MREG_ERROR_COUNT, 0);
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amvdec_write_dos(core, MREG_FATAL_ERROR, 0);
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amvdec_write_dos(core, MREG_WAIT_BUFFER, 0);
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sess->keyframe_found = 1;
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sess->priv = mpeg12;
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return 0;
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free_workspace:
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dma_free_coherent(core->dev, SIZE_WORKSPACE, mpeg12->workspace_vaddr,
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mpeg12->workspace_paddr);
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free_mpeg12:
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kfree(mpeg12);
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return ret;
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}
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static int codec_mpeg12_stop(struct amvdec_session *sess)
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{
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struct codec_mpeg12 *mpeg12 = sess->priv;
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struct amvdec_core *core = sess->core;
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if (mpeg12->workspace_vaddr)
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dma_free_coherent(core->dev, SIZE_WORKSPACE,
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mpeg12->workspace_vaddr,
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mpeg12->workspace_paddr);
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return 0;
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}
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static void codec_mpeg12_update_dar(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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u32 seq = amvdec_read_dos(core, MREG_SEQ_INFO);
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u32 ar = seq & MPEG2_SEQ_DAR_MASK;
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switch (ar) {
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case MPEG2_DAR_4_3:
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amvdec_set_par_from_dar(sess, 4, 3);
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break;
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case MPEG2_DAR_16_9:
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amvdec_set_par_from_dar(sess, 16, 9);
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break;
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case MPEG2_DAR_221_100:
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amvdec_set_par_from_dar(sess, 221, 100);
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break;
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default:
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sess->pixelaspect.numerator = 1;
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sess->pixelaspect.denominator = 1;
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break;
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}
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}
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static irqreturn_t codec_mpeg12_threaded_isr(struct amvdec_session *sess)
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{
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struct amvdec_core *core = sess->core;
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u32 reg;
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u32 pic_info;
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u32 is_progressive;
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u32 buffer_index;
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u32 field = V4L2_FIELD_NONE;
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u32 offset;
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amvdec_write_dos(core, ASSIST_MBOX1_CLR_REG, 1);
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reg = amvdec_read_dos(core, MREG_FATAL_ERROR);
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if (reg == 1) {
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dev_err(core->dev, "MPEG1/2 fatal error\n");
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amvdec_abort(sess);
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return IRQ_HANDLED;
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}
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reg = amvdec_read_dos(core, MREG_BUFFEROUT);
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if (!reg)
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return IRQ_HANDLED;
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/* Unclear what this means */
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if ((reg & GENMASK(23, 17)) == GENMASK(23, 17))
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goto end;
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pic_info = amvdec_read_dos(core, MREG_PIC_INFO);
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is_progressive = pic_info & PICINFO_PROG;
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if (!is_progressive)
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field = (pic_info & PICINFO_TOP_FIRST) ?
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V4L2_FIELD_INTERLACED_TB :
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V4L2_FIELD_INTERLACED_BT;
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codec_mpeg12_update_dar(sess);
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buffer_index = ((reg & 0xf) - 1) & 7;
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offset = amvdec_read_dos(core, MREG_FRAME_OFFSET);
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amvdec_dst_buf_done_idx(sess, buffer_index, offset, field);
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end:
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amvdec_write_dos(core, MREG_BUFFEROUT, 0);
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return IRQ_HANDLED;
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}
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static irqreturn_t codec_mpeg12_isr(struct amvdec_session *sess)
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{
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return IRQ_WAKE_THREAD;
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}
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struct amvdec_codec_ops codec_mpeg12_ops = {
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.start = codec_mpeg12_start,
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.stop = codec_mpeg12_stop,
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.isr = codec_mpeg12_isr,
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.threaded_isr = codec_mpeg12_threaded_isr,
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.can_recycle = codec_mpeg12_can_recycle,
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.recycle = codec_mpeg12_recycle,
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.eos_sequence = codec_mpeg12_eos_sequence,
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};
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