// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Maxime Jourdan <mjourdan@baylibre.com>
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*/
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#include <media/v4l2-mem2mem.h>
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#include <media/videobuf2-dma-contig.h>
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#include "codec_hevc_common.h"
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#include "vdec_helpers.h"
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#include "hevc_regs.h"
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#define MMU_COMPRESS_HEADER_SIZE 0x48000
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#define MMU_MAP_SIZE 0x4800
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const u16 vdec_hevc_parser_cmd[] = {
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0x0401, 0x8401, 0x0800, 0x0402,
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0x9002, 0x1423, 0x8CC3, 0x1423,
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0x8804, 0x9825, 0x0800, 0x04FE,
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0x8406, 0x8411, 0x1800, 0x8408,
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0x8409, 0x8C2A, 0x9C2B, 0x1C00,
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0x840F, 0x8407, 0x8000, 0x8408,
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0x2000, 0xA800, 0x8410, 0x04DE,
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0x840C, 0x840D, 0xAC00, 0xA000,
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0x08C0, 0x08E0, 0xA40E, 0xFC00,
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0x7C00
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};
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/* Configure decode head read mode */
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void codec_hevc_setup_decode_head(struct amvdec_session *sess, int is_10bit)
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{
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struct amvdec_core *core = sess->core;
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u32 body_size = amvdec_am21c_body_size(sess->width, sess->height);
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u32 head_size = amvdec_am21c_head_size(sess->width, sess->height);
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if (!codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
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/* Enable 2-plane reference read mode */
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amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(31));
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return;
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}
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if (codec_hevc_use_mmu(core->platform->revision,
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sess->pixfmt_cap, is_10bit))
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amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, BIT(4));
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else
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amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL1, 0);
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if (core->platform->revision < VDEC_REVISION_SM1)
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amvdec_write_dos(core, HEVCD_MPP_DECOMP_CTL2, body_size / 32);
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amvdec_write_dos(core, HEVC_CM_BODY_LENGTH, body_size);
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amvdec_write_dos(core, HEVC_CM_HEADER_OFFSET, body_size);
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amvdec_write_dos(core, HEVC_CM_HEADER_LENGTH, head_size);
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}
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EXPORT_SYMBOL_GPL(codec_hevc_setup_decode_head);
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static void codec_hevc_setup_buffers_gxbb(struct amvdec_session *sess,
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struct codec_hevc_common *comm,
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int is_10bit)
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{
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struct amvdec_core *core = sess->core;
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struct v4l2_m2m_buffer *buf;
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u32 buf_num = v4l2_m2m_num_dst_bufs_ready(sess->m2m_ctx);
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dma_addr_t buf_y_paddr = 0;
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dma_addr_t buf_uv_paddr = 0;
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u32 idx = 0;
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u32 val;
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int i;
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 0);
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v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
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struct vb2_buffer *vb = &buf->vb.vb2_buf;
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idx = vb->index;
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if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit))
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buf_y_paddr = comm->fbc_buffer_paddr[idx];
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else
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buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
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if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit)) {
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val = buf_y_paddr | (idx << 8) | 1;
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
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val);
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} else {
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buf_uv_paddr = vb2_dma_contig_plane_dma_addr(vb, 1);
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val = buf_y_paddr | ((idx * 2) << 8) | 1;
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
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val);
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val = buf_uv_paddr | ((idx * 2 + 1) << 8) | 1;
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR,
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val);
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}
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}
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if (codec_hevc_use_fbc(sess->pixfmt_cap, is_10bit))
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val = buf_y_paddr | (idx << 8) | 1;
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else
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val = buf_y_paddr | ((idx * 2) << 8) | 1;
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/* Fill the remaining unused slots with the last buffer's Y addr */
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for (i = buf_num; i < MAX_REF_PIC_NUM; ++i)
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CMD_ADDR, val);
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 1);
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amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
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for (i = 0; i < 32; ++i)
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amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
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}
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static void codec_hevc_setup_buffers_gxl(struct amvdec_session *sess,
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struct codec_hevc_common *comm,
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int is_10bit)
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{
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struct amvdec_core *core = sess->core;
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struct v4l2_m2m_buffer *buf;
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u32 revision = core->platform->revision;
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u32 pixfmt_cap = sess->pixfmt_cap;
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int i;
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR,
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BIT(2) | BIT(1));
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v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
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struct vb2_buffer *vb = &buf->vb.vb2_buf;
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dma_addr_t buf_y_paddr = 0;
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dma_addr_t buf_uv_paddr = 0;
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u32 idx = vb->index;
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if (codec_hevc_use_mmu(revision, pixfmt_cap, is_10bit))
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buf_y_paddr = comm->mmu_header_paddr[idx];
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else if (codec_hevc_use_downsample(pixfmt_cap, is_10bit))
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buf_y_paddr = comm->fbc_buffer_paddr[idx];
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else
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buf_y_paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
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buf_y_paddr >> 5);
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if (!codec_hevc_use_fbc(pixfmt_cap, is_10bit)) {
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buf_uv_paddr = vb2_dma_contig_plane_dma_addr(vb, 1);
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_DATA,
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buf_uv_paddr >> 5);
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}
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}
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amvdec_write_dos(core, HEVCD_MPP_ANC2AXI_TBL_CONF_ADDR, 1);
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amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_ACCCONFIG_ADDR, 1);
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for (i = 0; i < 32; ++i)
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amvdec_write_dos(core, HEVCD_MPP_ANC_CANVAS_DATA_ADDR, 0);
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}
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void codec_hevc_free_fbc_buffers(struct amvdec_session *sess,
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struct codec_hevc_common *comm)
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{
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struct device *dev = sess->core->dev;
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u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
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int i;
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for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
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if (comm->fbc_buffer_vaddr[i]) {
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dma_free_coherent(dev, am21_size,
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comm->fbc_buffer_vaddr[i],
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comm->fbc_buffer_paddr[i]);
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comm->fbc_buffer_vaddr[i] = NULL;
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}
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}
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}
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EXPORT_SYMBOL_GPL(codec_hevc_free_fbc_buffers);
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static int codec_hevc_alloc_fbc_buffers(struct amvdec_session *sess,
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struct codec_hevc_common *comm)
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{
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struct device *dev = sess->core->dev;
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struct v4l2_m2m_buffer *buf;
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u32 am21_size = amvdec_am21c_size(sess->width, sess->height);
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v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
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u32 idx = buf->vb.vb2_buf.index;
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dma_addr_t paddr;
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void *vaddr = dma_alloc_coherent(dev, am21_size, &paddr,
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GFP_KERNEL);
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if (!vaddr) {
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codec_hevc_free_fbc_buffers(sess, comm);
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return -ENOMEM;
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}
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comm->fbc_buffer_vaddr[idx] = vaddr;
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comm->fbc_buffer_paddr[idx] = paddr;
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}
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return 0;
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}
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void codec_hevc_free_mmu_headers(struct amvdec_session *sess,
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struct codec_hevc_common *comm)
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{
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struct device *dev = sess->core->dev;
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int i;
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for (i = 0; i < MAX_REF_PIC_NUM; ++i) {
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if (comm->mmu_header_vaddr[i]) {
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dma_free_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
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comm->mmu_header_vaddr[i],
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comm->mmu_header_paddr[i]);
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comm->mmu_header_vaddr[i] = NULL;
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}
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}
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if (comm->mmu_map_vaddr) {
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dma_free_coherent(dev, MMU_MAP_SIZE,
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comm->mmu_map_vaddr,
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comm->mmu_map_paddr);
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comm->mmu_map_vaddr = NULL;
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}
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}
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EXPORT_SYMBOL_GPL(codec_hevc_free_mmu_headers);
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static int codec_hevc_alloc_mmu_headers(struct amvdec_session *sess,
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struct codec_hevc_common *comm)
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{
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struct device *dev = sess->core->dev;
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struct v4l2_m2m_buffer *buf;
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comm->mmu_map_vaddr = dma_alloc_coherent(dev, MMU_MAP_SIZE,
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&comm->mmu_map_paddr,
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GFP_KERNEL);
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if (!comm->mmu_map_vaddr)
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return -ENOMEM;
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v4l2_m2m_for_each_dst_buf(sess->m2m_ctx, buf) {
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u32 idx = buf->vb.vb2_buf.index;
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dma_addr_t paddr;
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void *vaddr = dma_alloc_coherent(dev, MMU_COMPRESS_HEADER_SIZE,
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&paddr, GFP_KERNEL);
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if (!vaddr) {
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codec_hevc_free_mmu_headers(sess, comm);
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return -ENOMEM;
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}
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comm->mmu_header_vaddr[idx] = vaddr;
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comm->mmu_header_paddr[idx] = paddr;
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}
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return 0;
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}
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int codec_hevc_setup_buffers(struct amvdec_session *sess,
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struct codec_hevc_common *comm,
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int is_10bit)
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{
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struct amvdec_core *core = sess->core;
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int ret;
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if (codec_hevc_use_downsample(sess->pixfmt_cap, is_10bit)) {
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ret = codec_hevc_alloc_fbc_buffers(sess, comm);
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if (ret)
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return ret;
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}
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if (codec_hevc_use_mmu(core->platform->revision,
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sess->pixfmt_cap, is_10bit)) {
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ret = codec_hevc_alloc_mmu_headers(sess, comm);
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if (ret) {
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codec_hevc_free_fbc_buffers(sess, comm);
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return ret;
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}
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}
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if (core->platform->revision == VDEC_REVISION_GXBB)
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codec_hevc_setup_buffers_gxbb(sess, comm, is_10bit);
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else
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codec_hevc_setup_buffers_gxl(sess, comm, is_10bit);
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return 0;
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}
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EXPORT_SYMBOL_GPL(codec_hevc_setup_buffers);
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void codec_hevc_fill_mmu_map(struct amvdec_session *sess,
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struct codec_hevc_common *comm,
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struct vb2_buffer *vb)
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{
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u32 size = amvdec_am21c_size(sess->width, sess->height);
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u32 nb_pages = size / PAGE_SIZE;
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u32 *mmu_map = comm->mmu_map_vaddr;
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u32 first_page;
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u32 i;
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if (sess->pixfmt_cap == V4L2_PIX_FMT_NV12M)
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first_page = comm->fbc_buffer_paddr[vb->index] >> PAGE_SHIFT;
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else
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first_page = vb2_dma_contig_plane_dma_addr(vb, 0) >> PAGE_SHIFT;
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for (i = 0; i < nb_pages; ++i)
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mmu_map[i] = first_page + i;
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}
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EXPORT_SYMBOL_GPL(codec_hevc_fill_mmu_map);
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