// SPDX-License-Identifier: GPL-2.0
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/*
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* Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver
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*
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* Copyright (C) 2019 Linaro Ltd
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* Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
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*
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*/
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#include <linux/clk.h>
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#include <linux/debugfs.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/regulator/consumer.h>
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#include <linux/reset.h>
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#include <linux/spinlock.h>
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#include <media/v4l2-device.h>
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#include <media/v4l2-fwnode.h>
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#include <media/v4l2-mc.h>
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#include <media/v4l2-subdev.h>
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#define CSIS_DRIVER_NAME "imx7-mipi-csis"
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#define CSIS_SUBDEV_NAME CSIS_DRIVER_NAME
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#define CSIS_PAD_SINK 0
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#define CSIS_PAD_SOURCE 1
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#define CSIS_PADS_NUM 2
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#define MIPI_CSIS_DEF_PIX_WIDTH 640
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#define MIPI_CSIS_DEF_PIX_HEIGHT 480
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/* Register map definition */
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/* CSIS common control */
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#define MIPI_CSIS_CMN_CTRL 0x04
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#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW BIT(16)
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#define MIPI_CSIS_CMN_CTRL_INTER_MODE BIT(10)
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#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL BIT(2)
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#define MIPI_CSIS_CMN_CTRL_RESET BIT(1)
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#define MIPI_CSIS_CMN_CTRL_ENABLE BIT(0)
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#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET 8
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#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK (3 << 8)
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/* CSIS clock control */
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#define MIPI_CSIS_CLK_CTRL 0x08
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#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
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#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
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#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
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#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
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#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK (0xf << 4)
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#define MIPI_CSIS_CLK_CTRL_WCLK_SRC BIT(0)
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/* CSIS Interrupt mask */
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#define MIPI_CSIS_INTMSK 0x10
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#define MIPI_CSIS_INTMSK_EVEN_BEFORE BIT(31)
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#define MIPI_CSIS_INTMSK_EVEN_AFTER BIT(30)
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#define MIPI_CSIS_INTMSK_ODD_BEFORE BIT(29)
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#define MIPI_CSIS_INTMSK_ODD_AFTER BIT(28)
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#define MIPI_CSIS_INTMSK_FRAME_START BIT(24)
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#define MIPI_CSIS_INTMSK_FRAME_END BIT(20)
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#define MIPI_CSIS_INTMSK_ERR_SOT_HS BIT(16)
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#define MIPI_CSIS_INTMSK_ERR_LOST_FS BIT(12)
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#define MIPI_CSIS_INTMSK_ERR_LOST_FE BIT(8)
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#define MIPI_CSIS_INTMSK_ERR_OVER BIT(4)
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#define MIPI_CSIS_INTMSK_ERR_WRONG_CFG BIT(3)
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#define MIPI_CSIS_INTMSK_ERR_ECC BIT(2)
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#define MIPI_CSIS_INTMSK_ERR_CRC BIT(1)
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#define MIPI_CSIS_INTMSK_ERR_UNKNOWN BIT(0)
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/* CSIS Interrupt source */
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#define MIPI_CSIS_INTSRC 0x14
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#define MIPI_CSIS_INTSRC_EVEN_BEFORE BIT(31)
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#define MIPI_CSIS_INTSRC_EVEN_AFTER BIT(30)
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#define MIPI_CSIS_INTSRC_EVEN BIT(30)
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#define MIPI_CSIS_INTSRC_ODD_BEFORE BIT(29)
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#define MIPI_CSIS_INTSRC_ODD_AFTER BIT(28)
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#define MIPI_CSIS_INTSRC_ODD (0x3 << 28)
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#define MIPI_CSIS_INTSRC_NON_IMAGE_DATA (0xf << 28)
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#define MIPI_CSIS_INTSRC_FRAME_START BIT(24)
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#define MIPI_CSIS_INTSRC_FRAME_END BIT(20)
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#define MIPI_CSIS_INTSRC_ERR_SOT_HS BIT(16)
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#define MIPI_CSIS_INTSRC_ERR_LOST_FS BIT(12)
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#define MIPI_CSIS_INTSRC_ERR_LOST_FE BIT(8)
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#define MIPI_CSIS_INTSRC_ERR_OVER BIT(4)
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#define MIPI_CSIS_INTSRC_ERR_WRONG_CFG BIT(3)
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#define MIPI_CSIS_INTSRC_ERR_ECC BIT(2)
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#define MIPI_CSIS_INTSRC_ERR_CRC BIT(1)
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#define MIPI_CSIS_INTSRC_ERR_UNKNOWN BIT(0)
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#define MIPI_CSIS_INTSRC_ERRORS 0xfffff
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/* D-PHY status control */
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#define MIPI_CSIS_DPHYSTATUS 0x20
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#define MIPI_CSIS_DPHYSTATUS_ULPS_DAT BIT(8)
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#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_DAT BIT(4)
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#define MIPI_CSIS_DPHYSTATUS_ULPS_CLK BIT(1)
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#define MIPI_CSIS_DPHYSTATUS_STOPSTATE_CLK BIT(0)
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/* D-PHY common control */
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#define MIPI_CSIS_DPHYCTRL 0x24
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#define MIPI_CSIS_DPHYCTRL_HSS_MASK (0xff << 24)
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#define MIPI_CSIS_DPHYCTRL_HSS_OFFSET 24
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#define MIPI_CSIS_DPHYCTRL_SCLKS_MASK (0x3 << 22)
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#define MIPI_CSIS_DPHYCTRL_SCLKS_OFFSET 22
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#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_CLK BIT(6)
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#define MIPI_CSIS_DPHYCTRL_DPDN_SWAP_DAT BIT(5)
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#define MIPI_CSIS_DPHYCTRL_ENABLE_DAT BIT(1)
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#define MIPI_CSIS_DPHYCTRL_ENABLE_CLK BIT(0)
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#define MIPI_CSIS_DPHYCTRL_ENABLE (0x1f << 0)
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/* D-PHY Master and Slave Control register Low */
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#define MIPI_CSIS_DPHYBCTRL_L 0x30
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/* D-PHY Master and Slave Control register High */
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#define MIPI_CSIS_DPHYBCTRL_H 0x34
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/* D-PHY Slave Control register Low */
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#define MIPI_CSIS_DPHYSCTRL_L 0x38
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/* D-PHY Slave Control register High */
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#define MIPI_CSIS_DPHYSCTRL_H 0x3c
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/* ISP Configuration register */
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#define MIPI_CSIS_ISPCONFIG_CH0 0x40
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#define MIPI_CSIS_ISPCONFIG_CH1 0x50
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#define MIPI_CSIS_ISPCONFIG_CH2 0x60
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#define MIPI_CSIS_ISPCONFIG_CH3 0x70
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#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK (0xff << 24)
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#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x) ((x) << 24)
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#define MIPI_CSIS_ISPCFG_DOUBLE_CMPNT BIT(12)
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#define MIPI_CSIS_ISPCFG_ALIGN_32BIT BIT(11)
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#define MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT (0x1e << 2)
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#define MIPI_CSIS_ISPCFG_FMT_RAW8 (0x2a << 2)
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#define MIPI_CSIS_ISPCFG_FMT_RAW10 (0x2b << 2)
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#define MIPI_CSIS_ISPCFG_FMT_RAW12 (0x2c << 2)
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#define MIPI_CSIS_ISPCFG_FMT_RAW14 (0x2d << 2)
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/* User defined formats, x = 1...4 */
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#define MIPI_CSIS_ISPCFG_FMT_USER(x) ((0x30 + (x) - 1) << 2)
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#define MIPI_CSIS_ISPCFG_FMT_MASK (0x3f << 2)
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/* ISP Image Resolution register */
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#define MIPI_CSIS_ISPRESOL_CH0 0x44
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#define MIPI_CSIS_ISPRESOL_CH1 0x54
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#define MIPI_CSIS_ISPRESOL_CH2 0x64
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#define MIPI_CSIS_ISPRESOL_CH3 0x74
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#define CSIS_MAX_PIX_WIDTH 0xffff
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#define CSIS_MAX_PIX_HEIGHT 0xffff
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/* ISP SYNC register */
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#define MIPI_CSIS_ISPSYNC_CH0 0x48
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#define MIPI_CSIS_ISPSYNC_CH1 0x58
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#define MIPI_CSIS_ISPSYNC_CH2 0x68
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#define MIPI_CSIS_ISPSYNC_CH3 0x78
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#define MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET 18
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#define MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET 12
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#define MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET 0
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/* Non-image packet data buffers */
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#define MIPI_CSIS_PKTDATA_ODD 0x2000
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#define MIPI_CSIS_PKTDATA_EVEN 0x3000
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#define MIPI_CSIS_PKTDATA_SIZE SZ_4K
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#define DEFAULT_SCLK_CSIS_FREQ 166000000UL
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enum {
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ST_POWERED = 1,
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ST_STREAMING = 2,
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ST_SUSPENDED = 4,
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};
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struct mipi_csis_event {
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u32 mask;
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const char * const name;
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unsigned int counter;
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};
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static const struct mipi_csis_event mipi_csis_events[] = {
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/* Errors */
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{ MIPI_CSIS_INTSRC_ERR_SOT_HS, "SOT Error" },
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{ MIPI_CSIS_INTSRC_ERR_LOST_FS, "Lost Frame Start Error" },
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{ MIPI_CSIS_INTSRC_ERR_LOST_FE, "Lost Frame End Error" },
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{ MIPI_CSIS_INTSRC_ERR_OVER, "FIFO Overflow Error" },
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{ MIPI_CSIS_INTSRC_ERR_WRONG_CFG, "Wrong Configuration Error" },
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{ MIPI_CSIS_INTSRC_ERR_ECC, "ECC Error" },
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{ MIPI_CSIS_INTSRC_ERR_CRC, "CRC Error" },
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{ MIPI_CSIS_INTSRC_ERR_UNKNOWN, "Unknown Error" },
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/* Non-image data receive events */
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{ MIPI_CSIS_INTSRC_EVEN_BEFORE, "Non-image data before even frame" },
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{ MIPI_CSIS_INTSRC_EVEN_AFTER, "Non-image data after even frame" },
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{ MIPI_CSIS_INTSRC_ODD_BEFORE, "Non-image data before odd frame" },
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{ MIPI_CSIS_INTSRC_ODD_AFTER, "Non-image data after odd frame" },
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/* Frame start/end */
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{ MIPI_CSIS_INTSRC_FRAME_START, "Frame Start" },
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{ MIPI_CSIS_INTSRC_FRAME_END, "Frame End" },
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};
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#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
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static const char * const mipi_csis_clk_id[] = {"pclk", "wrap", "phy"};
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struct csis_hw_reset {
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struct regmap *src;
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u8 req_src;
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u8 rst_bit;
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};
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struct csi_state {
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/* lock elements below */
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struct mutex lock;
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/* lock for event handler */
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spinlock_t slock;
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struct device *dev;
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struct media_pad pads[CSIS_PADS_NUM];
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struct v4l2_subdev mipi_sd;
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struct v4l2_async_notifier notifier;
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struct v4l2_subdev *src_sd;
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u8 index;
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struct platform_device *pdev;
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struct phy *phy;
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void __iomem *regs;
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struct clk *wrap_clk;
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int irq;
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u32 flags;
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struct dentry *debugfs_root;
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bool debug;
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int num_clks;
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struct clk_bulk_data *clks;
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u32 clk_frequency;
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u32 hs_settle;
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struct reset_control *mrst;
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const struct csis_pix_format *csis_fmt;
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struct v4l2_mbus_framefmt format_mbus;
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struct v4l2_fwnode_bus_mipi_csi2 bus;
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struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
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struct csis_hw_reset hw_reset;
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struct regulator *mipi_phy_regulator;
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};
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struct csis_pix_format {
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u32 code;
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u32 fmt_reg;
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u8 width;
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};
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static const struct csis_pix_format mipi_csis_formats[] = {
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/* YUV formats. */
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{
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.code = MEDIA_BUS_FMT_UYVY8_2X8,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
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.width = 8,
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}, {
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.code = MEDIA_BUS_FMT_UYVY10_2X10,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_YCBCR422_8BIT,
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.width = 10,
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},
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/* RAW (Bayer and greyscale) formats. */
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{
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.code = MEDIA_BUS_FMT_SBGGR8_1X8,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
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.width = 8,
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}, {
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.code = MEDIA_BUS_FMT_SGBRG8_1X8,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
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.width = 8,
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}, {
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.code = MEDIA_BUS_FMT_SGRBG8_1X8,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
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.width = 8,
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}, {
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.code = MEDIA_BUS_FMT_SRGGB8_1X8,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
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.width = 8,
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}, {
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.code = MEDIA_BUS_FMT_Y8_1X8,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW8,
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.width = 8,
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}, {
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.code = MEDIA_BUS_FMT_SBGGR10_1X10,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
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.width = 10,
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}, {
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.code = MEDIA_BUS_FMT_SGBRG10_1X10,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
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.width = 10,
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}, {
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.code = MEDIA_BUS_FMT_SGRBG10_1X10,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
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.width = 10,
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}, {
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.code = MEDIA_BUS_FMT_SRGGB10_1X10,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
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.width = 10,
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}, {
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.code = MEDIA_BUS_FMT_Y10_1X10,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW10,
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.width = 10,
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}, {
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.code = MEDIA_BUS_FMT_SBGGR12_1X12,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
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.width = 12,
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}, {
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.code = MEDIA_BUS_FMT_SGBRG12_1X12,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
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.width = 12,
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}, {
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.code = MEDIA_BUS_FMT_SGRBG12_1X12,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
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.width = 12,
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}, {
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.code = MEDIA_BUS_FMT_SRGGB12_1X12,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
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.width = 12,
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}, {
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.code = MEDIA_BUS_FMT_Y12_1X12,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW12,
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.width = 12,
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}, {
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.code = MEDIA_BUS_FMT_SBGGR14_1X14,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
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.width = 14,
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}, {
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.code = MEDIA_BUS_FMT_SGBRG14_1X14,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
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.width = 14,
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}, {
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.code = MEDIA_BUS_FMT_SGRBG14_1X14,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
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.width = 14,
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}, {
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.code = MEDIA_BUS_FMT_SRGGB14_1X14,
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.fmt_reg = MIPI_CSIS_ISPCFG_FMT_RAW14,
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.width = 14,
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}
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};
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#define mipi_csis_write(__csis, __r, __v) writel(__v, (__csis)->regs + (__r))
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#define mipi_csis_read(__csis, __r) readl((__csis)->regs + (__r))
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static int mipi_csis_dump_regs(struct csi_state *state)
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{
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struct device *dev = &state->pdev->dev;
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unsigned int i;
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u32 cfg;
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static const struct {
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u32 offset;
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const char * const name;
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} registers[] = {
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{ 0x04, "CTRL" },
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{ 0x24, "DPHYCTRL" },
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{ 0x08, "CLKCTRL" },
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{ 0x20, "DPHYSTS" },
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{ 0x10, "INTMSK" },
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{ 0x40, "CONFIG_CH0" },
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{ 0x44, "RESOL_CH0" },
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{ 0xC0, "DBG_CONFIG" },
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{ 0x38, "DPHYSLAVE_L" },
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{ 0x3C, "DPHYSLAVE_H" },
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};
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dev_info(dev, "--- REGISTERS ---\n");
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for (i = 0; i < ARRAY_SIZE(registers); i++) {
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cfg = mipi_csis_read(state, registers[i].offset);
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dev_info(dev, "%12s: 0x%08x\n", registers[i].name, cfg);
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}
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return 0;
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}
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static struct csi_state *
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mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
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{
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return container_of(n, struct csi_state, notifier);
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}
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static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev)
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{
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return container_of(sdev, struct csi_state, mipi_sd);
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}
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static const struct csis_pix_format *find_csis_format(u32 code)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
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if (code == mipi_csis_formats[i].code)
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return &mipi_csis_formats[i];
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return NULL;
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}
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static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
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{
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mipi_csis_write(state, MIPI_CSIS_INTMSK, on ? 0xffffffff : 0);
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}
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static void mipi_csis_sw_reset(struct csi_state *state)
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{
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u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
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mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
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val | MIPI_CSIS_CMN_CTRL_RESET);
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usleep_range(10, 20);
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}
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static int mipi_csis_phy_init(struct csi_state *state)
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{
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state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy");
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if (IS_ERR(state->mipi_phy_regulator))
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return PTR_ERR(state->mipi_phy_regulator);
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return regulator_set_voltage(state->mipi_phy_regulator, 1000000,
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1000000);
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}
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static void mipi_csis_phy_reset(struct csi_state *state)
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{
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reset_control_assert(state->mrst);
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msleep(20);
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reset_control_deassert(state->mrst);
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}
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static void mipi_csis_system_enable(struct csi_state *state, int on)
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{
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u32 val, mask;
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val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
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if (on)
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val |= MIPI_CSIS_CMN_CTRL_ENABLE;
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else
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val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
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mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
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val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
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val &= ~MIPI_CSIS_DPHYCTRL_ENABLE;
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if (on) {
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mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
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val |= (mask & MIPI_CSIS_DPHYCTRL_ENABLE);
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}
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mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
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}
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/* Called with the state.lock mutex held */
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static void __mipi_csis_set_format(struct csi_state *state)
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{
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struct v4l2_mbus_framefmt *mf = &state->format_mbus;
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u32 val;
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/* Color format */
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val = mipi_csis_read(state, MIPI_CSIS_ISPCONFIG_CH0);
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val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK);
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val |= state->csis_fmt->fmt_reg;
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mipi_csis_write(state, MIPI_CSIS_ISPCONFIG_CH0, val);
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/* Pixel resolution */
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val = mf->width | (mf->height << 16);
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mipi_csis_write(state, MIPI_CSIS_ISPRESOL_CH0, val);
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}
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static void mipi_csis_set_hsync_settle(struct csi_state *state, int hs_settle)
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{
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u32 val = mipi_csis_read(state, MIPI_CSIS_DPHYCTRL);
|
|
val = (val & ~MIPI_CSIS_DPHYCTRL_HSS_MASK) | (hs_settle << 24);
|
|
mipi_csis_write(state, MIPI_CSIS_DPHYCTRL, val);
|
}
|
|
static void mipi_csis_set_params(struct csi_state *state)
|
{
|
int lanes = state->bus.num_data_lanes;
|
u32 val;
|
|
val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
|
val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
|
val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
|
val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
|
mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
|
|
__mipi_csis_set_format(state);
|
|
mipi_csis_set_hsync_settle(state, state->hs_settle);
|
|
val = (0 << MIPI_CSIS_ISPSYNC_HSYNC_LINTV_OFFSET) |
|
(0 << MIPI_CSIS_ISPSYNC_VSYNC_SINTV_OFFSET) |
|
(0 << MIPI_CSIS_ISPSYNC_VSYNC_EINTV_OFFSET);
|
mipi_csis_write(state, MIPI_CSIS_ISPSYNC_CH0, val);
|
|
val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
|
val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
|
if (state->wrap_clk)
|
val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
|
else
|
val &= ~MIPI_CSIS_CLK_CTRL_WCLK_SRC;
|
|
val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
|
val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
|
mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val);
|
|
mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_L, 0x1f4);
|
mipi_csis_write(state, MIPI_CSIS_DPHYBCTRL_H, 0);
|
|
/* Update the shadow register. */
|
val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
|
mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
|
val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
|
MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
|
}
|
|
static int mipi_csis_clk_enable(struct csi_state *state)
|
{
|
return clk_bulk_prepare_enable(state->num_clks, state->clks);
|
}
|
|
static void mipi_csis_clk_disable(struct csi_state *state)
|
{
|
clk_bulk_disable_unprepare(state->num_clks, state->clks);
|
}
|
|
static int mipi_csis_clk_get(struct csi_state *state)
|
{
|
struct device *dev = &state->pdev->dev;
|
unsigned int i;
|
int ret;
|
|
state->num_clks = ARRAY_SIZE(mipi_csis_clk_id);
|
state->clks = devm_kcalloc(dev, state->num_clks, sizeof(*state->clks),
|
GFP_KERNEL);
|
|
if (!state->clks)
|
return -ENOMEM;
|
|
for (i = 0; i < state->num_clks; i++)
|
state->clks[i].id = mipi_csis_clk_id[i];
|
|
ret = devm_clk_bulk_get(dev, state->num_clks, state->clks);
|
if (ret < 0)
|
return ret;
|
|
state->wrap_clk = devm_clk_get(dev, "wrap");
|
if (IS_ERR(state->wrap_clk))
|
return PTR_ERR(state->wrap_clk);
|
|
/* Set clock rate */
|
ret = clk_set_rate(state->wrap_clk, state->clk_frequency);
|
if (ret < 0)
|
dev_err(dev, "set rate=%d failed: %d\n", state->clk_frequency,
|
ret);
|
|
return ret;
|
}
|
|
static void mipi_csis_start_stream(struct csi_state *state)
|
{
|
mipi_csis_sw_reset(state);
|
mipi_csis_set_params(state);
|
mipi_csis_system_enable(state, true);
|
mipi_csis_enable_interrupts(state, true);
|
}
|
|
static void mipi_csis_stop_stream(struct csi_state *state)
|
{
|
mipi_csis_enable_interrupts(state, false);
|
mipi_csis_system_enable(state, false);
|
}
|
|
static void mipi_csis_clear_counters(struct csi_state *state)
|
{
|
unsigned long flags;
|
unsigned int i;
|
|
spin_lock_irqsave(&state->slock, flags);
|
for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
|
state->events[i].counter = 0;
|
spin_unlock_irqrestore(&state->slock, flags);
|
}
|
|
static void mipi_csis_log_counters(struct csi_state *state, bool non_errors)
|
{
|
unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
|
: MIPI_CSIS_NUM_EVENTS - 6;
|
struct device *dev = &state->pdev->dev;
|
unsigned long flags;
|
unsigned int i;
|
|
spin_lock_irqsave(&state->slock, flags);
|
|
for (i = 0; i < num_events; ++i) {
|
if (state->events[i].counter > 0 || state->debug)
|
dev_info(dev, "%s events: %d\n", state->events[i].name,
|
state->events[i].counter);
|
}
|
spin_unlock_irqrestore(&state->slock, flags);
|
}
|
|
/*
|
* V4L2 subdev operations
|
*/
|
static int mipi_csis_s_stream(struct v4l2_subdev *mipi_sd, int enable)
|
{
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
int ret = 0;
|
|
if (enable) {
|
mipi_csis_clear_counters(state);
|
ret = pm_runtime_get_sync(&state->pdev->dev);
|
if (ret < 0) {
|
pm_runtime_put_noidle(&state->pdev->dev);
|
return ret;
|
}
|
ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
|
if (ret < 0)
|
return ret;
|
}
|
|
mutex_lock(&state->lock);
|
if (enable) {
|
if (state->flags & ST_SUSPENDED) {
|
ret = -EBUSY;
|
goto unlock;
|
}
|
|
mipi_csis_start_stream(state);
|
ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
|
if (ret < 0)
|
goto unlock;
|
|
mipi_csis_log_counters(state, true);
|
|
state->flags |= ST_STREAMING;
|
} else {
|
v4l2_subdev_call(state->src_sd, video, s_stream, 0);
|
ret = v4l2_subdev_call(state->src_sd, core, s_power, 0);
|
mipi_csis_stop_stream(state);
|
state->flags &= ~ST_STREAMING;
|
if (state->debug)
|
mipi_csis_log_counters(state, true);
|
}
|
|
unlock:
|
mutex_unlock(&state->lock);
|
if (!enable)
|
pm_runtime_put(&state->pdev->dev);
|
|
return ret;
|
}
|
|
static int mipi_csis_link_setup(struct media_entity *entity,
|
const struct media_pad *local_pad,
|
const struct media_pad *remote_pad, u32 flags)
|
{
|
struct v4l2_subdev *mipi_sd = media_entity_to_v4l2_subdev(entity);
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
struct v4l2_subdev *remote_sd;
|
int ret = 0;
|
|
dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name,
|
local_pad->entity->name);
|
|
remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
|
|
mutex_lock(&state->lock);
|
|
if (local_pad->flags & MEDIA_PAD_FL_SINK) {
|
if (flags & MEDIA_LNK_FL_ENABLED) {
|
if (state->src_sd) {
|
ret = -EBUSY;
|
goto out;
|
}
|
state->src_sd = remote_sd;
|
} else {
|
state->src_sd = NULL;
|
}
|
}
|
|
out:
|
mutex_unlock(&state->lock);
|
return ret;
|
}
|
|
static struct v4l2_mbus_framefmt *
|
mipi_csis_get_format(struct csi_state *state,
|
struct v4l2_subdev_pad_config *cfg,
|
enum v4l2_subdev_format_whence which,
|
unsigned int pad)
|
{
|
if (which == V4L2_SUBDEV_FORMAT_TRY)
|
return v4l2_subdev_get_try_format(&state->mipi_sd, cfg, pad);
|
|
return &state->format_mbus;
|
}
|
|
static int mipi_csis_init_cfg(struct v4l2_subdev *mipi_sd,
|
struct v4l2_subdev_pad_config *cfg)
|
{
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
struct v4l2_mbus_framefmt *fmt_sink;
|
struct v4l2_mbus_framefmt *fmt_source;
|
enum v4l2_subdev_format_whence which;
|
|
which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
|
fmt_sink = mipi_csis_get_format(state, cfg, which, CSIS_PAD_SINK);
|
|
fmt_sink->code = MEDIA_BUS_FMT_UYVY8_2X8;
|
fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH;
|
fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT;
|
fmt_sink->field = V4L2_FIELD_NONE;
|
|
fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M;
|
fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
|
fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
|
fmt_sink->quantization =
|
V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
|
fmt_sink->ycbcr_enc);
|
|
/*
|
* When called from mipi_csis_subdev_init() to initialize the active
|
* configuration, cfg is NULL, which indicates there's no source pad
|
* configuration to set.
|
*/
|
if (!cfg)
|
return 0;
|
|
fmt_source = mipi_csis_get_format(state, cfg, which, CSIS_PAD_SOURCE);
|
*fmt_source = *fmt_sink;
|
|
return 0;
|
}
|
|
static int mipi_csis_get_fmt(struct v4l2_subdev *mipi_sd,
|
struct v4l2_subdev_pad_config *cfg,
|
struct v4l2_subdev_format *sdformat)
|
{
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
struct v4l2_mbus_framefmt *fmt;
|
|
mutex_lock(&state->lock);
|
fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
|
sdformat->format = *fmt;
|
mutex_unlock(&state->lock);
|
|
return 0;
|
}
|
|
static int mipi_csis_enum_mbus_code(struct v4l2_subdev *mipi_sd,
|
struct v4l2_subdev_pad_config *cfg,
|
struct v4l2_subdev_mbus_code_enum *code)
|
{
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
|
/*
|
* The CSIS can't transcode in any way, the source format is identical
|
* to the sink format.
|
*/
|
if (code->pad == CSIS_PAD_SOURCE) {
|
struct v4l2_mbus_framefmt *fmt;
|
|
if (code->index > 0)
|
return -EINVAL;
|
|
fmt = mipi_csis_get_format(state, cfg, code->which, code->pad);
|
code->code = fmt->code;
|
return 0;
|
}
|
|
if (code->pad != CSIS_PAD_SINK)
|
return -EINVAL;
|
|
if (code->index >= ARRAY_SIZE(mipi_csis_formats))
|
return -EINVAL;
|
|
code->code = mipi_csis_formats[code->index].code;
|
|
return 0;
|
}
|
|
static int mipi_csis_set_fmt(struct v4l2_subdev *mipi_sd,
|
struct v4l2_subdev_pad_config *cfg,
|
struct v4l2_subdev_format *sdformat)
|
{
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
struct csis_pix_format const *csis_fmt;
|
struct v4l2_mbus_framefmt *fmt;
|
unsigned int align;
|
|
/*
|
* The CSIS can't transcode in any way, the source format can't be
|
* modified.
|
*/
|
if (sdformat->pad == CSIS_PAD_SOURCE)
|
return mipi_csis_get_fmt(mipi_sd, cfg, sdformat);
|
|
if (sdformat->pad != CSIS_PAD_SINK)
|
return -EINVAL;
|
|
fmt = mipi_csis_get_format(state, cfg, sdformat->which, sdformat->pad);
|
|
mutex_lock(&state->lock);
|
|
/* Validate the media bus code and clamp the size. */
|
csis_fmt = find_csis_format(sdformat->format.code);
|
if (!csis_fmt)
|
csis_fmt = &mipi_csis_formats[0];
|
|
fmt->code = csis_fmt->code;
|
fmt->width = sdformat->format.width;
|
fmt->height = sdformat->format.height;
|
|
/*
|
* The total number of bits per line must be a multiple of 8. We thus
|
* need to align the width for formats that are not multiples of 8
|
* bits.
|
*/
|
switch (csis_fmt->width % 8) {
|
case 0:
|
align = 1;
|
break;
|
case 4:
|
align = 2;
|
break;
|
case 2:
|
case 6:
|
align = 4;
|
break;
|
case 1:
|
case 3:
|
case 5:
|
case 7:
|
align = 8;
|
break;
|
}
|
|
v4l_bound_align_image(&fmt->width, 1, CSIS_MAX_PIX_WIDTH, align,
|
&fmt->height, 1, CSIS_MAX_PIX_HEIGHT, 1, 0);
|
|
sdformat->format = *fmt;
|
|
/* Propagate the format from sink to source. */
|
fmt = mipi_csis_get_format(state, cfg, sdformat->which,
|
CSIS_PAD_SOURCE);
|
*fmt = sdformat->format;
|
|
/* Store the CSIS format descriptor for active formats. */
|
if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
|
state->csis_fmt = csis_fmt;
|
|
mutex_unlock(&state->lock);
|
|
return 0;
|
}
|
|
static int mipi_csis_log_status(struct v4l2_subdev *mipi_sd)
|
{
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
|
mutex_lock(&state->lock);
|
mipi_csis_log_counters(state, true);
|
if (state->debug && (state->flags & ST_POWERED))
|
mipi_csis_dump_regs(state);
|
mutex_unlock(&state->lock);
|
|
return 0;
|
}
|
|
static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
|
{
|
struct csi_state *state = dev_id;
|
unsigned long flags;
|
unsigned int i;
|
u32 status;
|
|
status = mipi_csis_read(state, MIPI_CSIS_INTSRC);
|
|
spin_lock_irqsave(&state->slock, flags);
|
|
/* Update the event/error counters */
|
if ((status & MIPI_CSIS_INTSRC_ERRORS) || state->debug) {
|
for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
|
if (!(status & state->events[i].mask))
|
continue;
|
state->events[i].counter++;
|
}
|
}
|
spin_unlock_irqrestore(&state->slock, flags);
|
|
mipi_csis_write(state, MIPI_CSIS_INTSRC, status);
|
|
return IRQ_HANDLED;
|
}
|
|
static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
|
.log_status = mipi_csis_log_status,
|
};
|
|
static const struct media_entity_operations mipi_csis_entity_ops = {
|
.link_setup = mipi_csis_link_setup,
|
.link_validate = v4l2_subdev_link_validate,
|
.get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
|
};
|
|
static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
|
.s_stream = mipi_csis_s_stream,
|
};
|
|
static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
|
.init_cfg = mipi_csis_init_cfg,
|
.enum_mbus_code = mipi_csis_enum_mbus_code,
|
.get_fmt = mipi_csis_get_fmt,
|
.set_fmt = mipi_csis_set_fmt,
|
};
|
|
static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
|
.core = &mipi_csis_core_ops,
|
.video = &mipi_csis_video_ops,
|
.pad = &mipi_csis_pad_ops,
|
};
|
|
static int mipi_csis_parse_dt(struct platform_device *pdev,
|
struct csi_state *state)
|
{
|
struct device_node *node = pdev->dev.of_node;
|
|
if (of_property_read_u32(node, "clock-frequency",
|
&state->clk_frequency))
|
state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
|
|
/* Get MIPI PHY resets */
|
state->mrst = devm_reset_control_get_exclusive(&pdev->dev, "mrst");
|
if (IS_ERR(state->mrst))
|
return PTR_ERR(state->mrst);
|
|
/* Get MIPI CSI-2 bus configuration from the endpoint node. */
|
of_property_read_u32(node, "fsl,csis-hs-settle", &state->hs_settle);
|
|
return 0;
|
}
|
|
static int mipi_csis_pm_resume(struct device *dev, bool runtime);
|
|
static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
|
struct v4l2_subdev *sd,
|
struct v4l2_async_subdev *asd)
|
{
|
struct csi_state *state = mipi_notifier_to_csis_state(notifier);
|
struct media_pad *sink = &state->mipi_sd.entity.pads[CSIS_PAD_SINK];
|
|
return v4l2_create_fwnode_links_to_pad(sd, sink);
|
}
|
|
static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
|
.bound = mipi_csis_notify_bound,
|
};
|
|
static int mipi_csis_subdev_init(struct v4l2_subdev *mipi_sd,
|
struct platform_device *pdev,
|
const struct v4l2_subdev_ops *ops)
|
{
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
|
v4l2_subdev_init(mipi_sd, ops);
|
mipi_sd->owner = THIS_MODULE;
|
snprintf(mipi_sd->name, sizeof(mipi_sd->name), "%s.%d",
|
CSIS_SUBDEV_NAME, state->index);
|
|
mipi_sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
|
mipi_sd->ctrl_handler = NULL;
|
|
mipi_sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
|
mipi_sd->entity.ops = &mipi_csis_entity_ops;
|
|
mipi_sd->dev = &pdev->dev;
|
|
state->csis_fmt = &mipi_csis_formats[0];
|
mipi_csis_init_cfg(mipi_sd, NULL);
|
|
v4l2_set_subdevdata(mipi_sd, &pdev->dev);
|
|
state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
|
state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
|
return media_entity_pads_init(&mipi_sd->entity, CSIS_PADS_NUM,
|
state->pads);
|
}
|
|
static int mipi_csis_async_register(struct csi_state *state)
|
{
|
struct v4l2_fwnode_endpoint vep = {
|
.bus_type = V4L2_MBUS_CSI2_DPHY,
|
};
|
struct v4l2_async_subdev *asd;
|
struct fwnode_handle *ep;
|
int ret;
|
|
v4l2_async_notifier_init(&state->notifier);
|
|
ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
|
FWNODE_GRAPH_ENDPOINT_NEXT);
|
if (!ep)
|
return -ENOTCONN;
|
|
ret = v4l2_fwnode_endpoint_parse(ep, &vep);
|
if (ret)
|
goto err_parse;
|
|
state->bus = vep.bus.mipi_csi2;
|
|
dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes);
|
dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags);
|
|
asd = v4l2_async_notifier_add_fwnode_remote_subdev(
|
&state->notifier, ep, sizeof(*asd));
|
if (IS_ERR(asd)) {
|
ret = PTR_ERR(asd);
|
goto err_parse;
|
}
|
|
fwnode_handle_put(ep);
|
|
state->notifier.ops = &mipi_csis_notify_ops;
|
|
ret = v4l2_async_subdev_notifier_register(&state->mipi_sd,
|
&state->notifier);
|
if (ret)
|
return ret;
|
|
return v4l2_async_register_subdev(&state->mipi_sd);
|
|
err_parse:
|
fwnode_handle_put(ep);
|
|
return ret;
|
}
|
|
static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
|
{
|
struct csi_state *state = m->private;
|
|
return mipi_csis_dump_regs(state);
|
}
|
DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
|
|
static void mipi_csis_debugfs_init(struct csi_state *state)
|
{
|
state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL);
|
|
debugfs_create_bool("debug_enable", 0600, state->debugfs_root,
|
&state->debug);
|
debugfs_create_file("dump_regs", 0600, state->debugfs_root, state,
|
&mipi_csis_dump_regs_fops);
|
}
|
|
static void mipi_csis_debugfs_exit(struct csi_state *state)
|
{
|
debugfs_remove_recursive(state->debugfs_root);
|
}
|
|
static int mipi_csis_probe(struct platform_device *pdev)
|
{
|
struct device *dev = &pdev->dev;
|
struct csi_state *state;
|
int ret;
|
|
state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
|
if (!state)
|
return -ENOMEM;
|
|
spin_lock_init(&state->slock);
|
|
state->pdev = pdev;
|
state->dev = dev;
|
|
ret = mipi_csis_parse_dt(pdev, state);
|
if (ret < 0) {
|
dev_err(dev, "Failed to parse device tree: %d\n", ret);
|
return ret;
|
}
|
|
ret = mipi_csis_phy_init(state);
|
if (ret < 0)
|
return ret;
|
|
mipi_csis_phy_reset(state);
|
|
state->regs = devm_platform_ioremap_resource(pdev, 0);
|
if (IS_ERR(state->regs))
|
return PTR_ERR(state->regs);
|
|
state->irq = platform_get_irq(pdev, 0);
|
if (state->irq < 0)
|
return state->irq;
|
|
ret = mipi_csis_clk_get(state);
|
if (ret < 0)
|
return ret;
|
|
ret = mipi_csis_clk_enable(state);
|
if (ret < 0) {
|
dev_err(state->dev, "failed to enable clocks: %d\n", ret);
|
return ret;
|
}
|
|
ret = devm_request_irq(dev, state->irq, mipi_csis_irq_handler,
|
0, dev_name(dev), state);
|
if (ret) {
|
dev_err(dev, "Interrupt request failed\n");
|
goto disable_clock;
|
}
|
|
platform_set_drvdata(pdev, &state->mipi_sd);
|
|
mutex_init(&state->lock);
|
ret = mipi_csis_subdev_init(&state->mipi_sd, pdev,
|
&mipi_csis_subdev_ops);
|
if (ret < 0)
|
goto disable_clock;
|
|
ret = mipi_csis_async_register(state);
|
if (ret < 0) {
|
dev_err(&pdev->dev, "async register failed: %d\n", ret);
|
goto cleanup;
|
}
|
|
memcpy(state->events, mipi_csis_events, sizeof(state->events));
|
|
mipi_csis_debugfs_init(state);
|
pm_runtime_enable(dev);
|
if (!pm_runtime_enabled(dev)) {
|
ret = mipi_csis_pm_resume(dev, true);
|
if (ret < 0)
|
goto unregister_all;
|
}
|
|
dev_info(&pdev->dev, "lanes: %d, hs_settle: %d, wclk: %d, freq: %u\n",
|
state->bus.num_data_lanes, state->hs_settle,
|
state->wrap_clk ? 1 : 0, state->clk_frequency);
|
|
return 0;
|
|
unregister_all:
|
mipi_csis_debugfs_exit(state);
|
cleanup:
|
media_entity_cleanup(&state->mipi_sd.entity);
|
v4l2_async_notifier_unregister(&state->notifier);
|
v4l2_async_notifier_cleanup(&state->notifier);
|
v4l2_async_unregister_subdev(&state->mipi_sd);
|
disable_clock:
|
mipi_csis_clk_disable(state);
|
mutex_destroy(&state->lock);
|
|
return ret;
|
}
|
|
static int mipi_csis_pm_suspend(struct device *dev, bool runtime)
|
{
|
struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
int ret = 0;
|
|
mutex_lock(&state->lock);
|
if (state->flags & ST_POWERED) {
|
mipi_csis_stop_stream(state);
|
ret = regulator_disable(state->mipi_phy_regulator);
|
if (ret)
|
goto unlock;
|
mipi_csis_clk_disable(state);
|
state->flags &= ~ST_POWERED;
|
if (!runtime)
|
state->flags |= ST_SUSPENDED;
|
}
|
|
unlock:
|
mutex_unlock(&state->lock);
|
|
return ret ? -EAGAIN : 0;
|
}
|
|
static int mipi_csis_pm_resume(struct device *dev, bool runtime)
|
{
|
struct v4l2_subdev *mipi_sd = dev_get_drvdata(dev);
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
int ret = 0;
|
|
mutex_lock(&state->lock);
|
if (!runtime && !(state->flags & ST_SUSPENDED))
|
goto unlock;
|
|
if (!(state->flags & ST_POWERED)) {
|
ret = regulator_enable(state->mipi_phy_regulator);
|
if (ret)
|
goto unlock;
|
|
state->flags |= ST_POWERED;
|
mipi_csis_clk_enable(state);
|
}
|
if (state->flags & ST_STREAMING)
|
mipi_csis_start_stream(state);
|
|
state->flags &= ~ST_SUSPENDED;
|
|
unlock:
|
mutex_unlock(&state->lock);
|
|
return ret ? -EAGAIN : 0;
|
}
|
|
static int __maybe_unused mipi_csis_suspend(struct device *dev)
|
{
|
return mipi_csis_pm_suspend(dev, false);
|
}
|
|
static int __maybe_unused mipi_csis_resume(struct device *dev)
|
{
|
return mipi_csis_pm_resume(dev, false);
|
}
|
|
static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
|
{
|
return mipi_csis_pm_suspend(dev, true);
|
}
|
|
static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
|
{
|
return mipi_csis_pm_resume(dev, true);
|
}
|
|
static int mipi_csis_remove(struct platform_device *pdev)
|
{
|
struct v4l2_subdev *mipi_sd = platform_get_drvdata(pdev);
|
struct csi_state *state = mipi_sd_to_csis_state(mipi_sd);
|
|
mipi_csis_debugfs_exit(state);
|
v4l2_async_notifier_unregister(&state->notifier);
|
v4l2_async_notifier_cleanup(&state->notifier);
|
v4l2_async_unregister_subdev(&state->mipi_sd);
|
|
pm_runtime_disable(&pdev->dev);
|
mipi_csis_pm_suspend(&pdev->dev, true);
|
mipi_csis_clk_disable(state);
|
media_entity_cleanup(&state->mipi_sd.entity);
|
mutex_destroy(&state->lock);
|
pm_runtime_set_suspended(&pdev->dev);
|
|
return 0;
|
}
|
|
static const struct dev_pm_ops mipi_csis_pm_ops = {
|
SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
|
NULL)
|
SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume)
|
};
|
|
static const struct of_device_id mipi_csis_of_match[] = {
|
{ .compatible = "fsl,imx7-mipi-csi2", },
|
{ /* sentinel */ },
|
};
|
MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
|
|
static struct platform_driver mipi_csis_driver = {
|
.probe = mipi_csis_probe,
|
.remove = mipi_csis_remove,
|
.driver = {
|
.of_match_table = mipi_csis_of_match,
|
.name = CSIS_DRIVER_NAME,
|
.pm = &mipi_csis_pm_ops,
|
},
|
};
|
|
module_platform_driver(mipi_csis_driver);
|
|
MODULE_DESCRIPTION("i.MX7 MIPI CSI-2 Receiver driver");
|
MODULE_LICENSE("GPL v2");
|
MODULE_ALIAS("platform:imx7-mipi-csi2");
|
