// SPDX-License-Identifier: GPL-2.0
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/*
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* Support for Intel Camera Imaging ISP subsystem.
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* Copyright (c) 2010 - 2015, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#define __INLINE_INPUT_SYSTEM__
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#include "input_system.h"
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#include "assert_support.h"
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#include "ia_css_isys.h"
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#include "ia_css_irq.h"
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#include "sh_css_internal.h"
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#if !defined(ISP2401)
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void ia_css_isys_rx_enable_all_interrupts(enum mipi_port_id port)
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{
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hrt_data bits = receiver_port_reg_load(RX0_ID,
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port,
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_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
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bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT) |
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/*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT) | */
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT) |
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(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT);
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/*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT); */
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receiver_port_reg_store(RX0_ID,
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port,
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_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits);
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/*
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* The CSI is nested into the Iunit IRQ's
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*/
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ia_css_irq_enable(IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR, true);
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return;
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}
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/* This function converts between the enum used on the CSS API and the
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* internal DLI enum type.
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* We do not use an array for this since we cannot use named array
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* initializers in Windows. Without that there is no easy way to guarantee
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* that the array values would be in the correct order.
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* */
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enum mipi_port_id ia_css_isys_port_to_mipi_port(enum mipi_port_id api_port)
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{
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/* In this module the validity of the inptu variable should
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* have been checked already, so we do not check for erroneous
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* values. */
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enum mipi_port_id port = MIPI_PORT0_ID;
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if (api_port == MIPI_PORT1_ID)
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port = MIPI_PORT1_ID;
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else if (api_port == MIPI_PORT2_ID)
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port = MIPI_PORT2_ID;
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return port;
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}
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unsigned int ia_css_isys_rx_get_interrupt_reg(enum mipi_port_id port)
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{
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return receiver_port_reg_load(RX0_ID,
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port,
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_HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
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}
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void ia_css_rx_get_irq_info(unsigned int *irq_infos)
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{
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ia_css_rx_port_get_irq_info(MIPI_PORT1_ID, irq_infos);
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}
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void ia_css_rx_port_get_irq_info(enum mipi_port_id api_port,
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unsigned int *irq_infos)
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{
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enum mipi_port_id port = ia_css_isys_port_to_mipi_port(api_port);
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ia_css_isys_rx_get_irq_info(port, irq_infos);
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}
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void ia_css_isys_rx_get_irq_info(enum mipi_port_id port,
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unsigned int *irq_infos)
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{
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unsigned int bits;
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assert(irq_infos);
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bits = ia_css_isys_rx_get_interrupt_reg(port);
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*irq_infos = ia_css_isys_rx_translate_irq_infos(bits);
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}
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/* Translate register bits to CSS API enum mask */
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unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits)
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{
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unsigned int infos = 0;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ECC_CORRECTED;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_CONTROL;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_CRC;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC;
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if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT))
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infos |= IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC;
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return infos;
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}
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void ia_css_rx_clear_irq_info(unsigned int irq_infos)
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{
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ia_css_rx_port_clear_irq_info(MIPI_PORT1_ID, irq_infos);
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}
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void ia_css_rx_port_clear_irq_info(enum mipi_port_id api_port,
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unsigned int irq_infos)
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{
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enum mipi_port_id port = ia_css_isys_port_to_mipi_port(api_port);
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ia_css_isys_rx_clear_irq_info(port, irq_infos);
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}
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void ia_css_isys_rx_clear_irq_info(enum mipi_port_id port,
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unsigned int irq_infos)
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{
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hrt_data bits = receiver_port_reg_load(RX0_ID,
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port,
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_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
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/* MW: Why do we remap the receiver bitmap */
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if (irq_infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ECC_CORRECTED)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT;
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if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
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bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT;
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receiver_port_reg_store(RX0_ID,
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port,
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_HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits);
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return;
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}
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#endif /* #if !defined(ISP2401) */
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int ia_css_isys_convert_stream_format_to_mipi_format(
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enum atomisp_input_format input_format,
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mipi_predictor_t compression,
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unsigned int *fmt_type)
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{
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assert(fmt_type);
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/*
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* Custom (user defined) modes. Used for compressed
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* MIPI transfers
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*
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* Checkpatch thinks the indent before "if" is suspect
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* I think the only suspect part is the missing "else"
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* because of the return.
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*/
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if (compression != MIPI_PREDICTOR_NONE) {
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switch (input_format) {
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case ATOMISP_INPUT_FORMAT_RAW_6:
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*fmt_type = 6;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_7:
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*fmt_type = 7;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_8:
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*fmt_type = 8;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_10:
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*fmt_type = 10;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_12:
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*fmt_type = 12;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_14:
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*fmt_type = 14;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_16:
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*fmt_type = 16;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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/*
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* This mapping comes from the Arasan CSS function spec
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* (CSS_func_spec1.08_ahb_sep29_08.pdf).
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*
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* MW: For some reason the mapping is not 1-to-1
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*/
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switch (input_format) {
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case ATOMISP_INPUT_FORMAT_RGB_888:
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*fmt_type = MIPI_FORMAT_RGB888;
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break;
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case ATOMISP_INPUT_FORMAT_RGB_555:
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*fmt_type = MIPI_FORMAT_RGB555;
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break;
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case ATOMISP_INPUT_FORMAT_RGB_444:
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*fmt_type = MIPI_FORMAT_RGB444;
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break;
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case ATOMISP_INPUT_FORMAT_RGB_565:
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*fmt_type = MIPI_FORMAT_RGB565;
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break;
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case ATOMISP_INPUT_FORMAT_RGB_666:
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*fmt_type = MIPI_FORMAT_RGB666;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_8:
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*fmt_type = MIPI_FORMAT_RAW8;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_10:
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*fmt_type = MIPI_FORMAT_RAW10;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_6:
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*fmt_type = MIPI_FORMAT_RAW6;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_7:
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*fmt_type = MIPI_FORMAT_RAW7;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_12:
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*fmt_type = MIPI_FORMAT_RAW12;
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break;
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case ATOMISP_INPUT_FORMAT_RAW_14:
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*fmt_type = MIPI_FORMAT_RAW14;
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break;
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case ATOMISP_INPUT_FORMAT_YUV420_8:
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*fmt_type = MIPI_FORMAT_YUV420_8;
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break;
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case ATOMISP_INPUT_FORMAT_YUV420_10:
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*fmt_type = MIPI_FORMAT_YUV420_10;
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break;
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case ATOMISP_INPUT_FORMAT_YUV422_8:
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*fmt_type = MIPI_FORMAT_YUV422_8;
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break;
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case ATOMISP_INPUT_FORMAT_YUV422_10:
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*fmt_type = MIPI_FORMAT_YUV422_10;
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break;
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case ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY:
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*fmt_type = MIPI_FORMAT_YUV420_8_LEGACY;
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break;
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case ATOMISP_INPUT_FORMAT_EMBEDDED:
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*fmt_type = MIPI_FORMAT_EMBEDDED;
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break;
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#ifndef ISP2401
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case ATOMISP_INPUT_FORMAT_RAW_16:
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/* This is not specified by Arasan, so we use
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* 17 for now.
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*/
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*fmt_type = MIPI_FORMAT_RAW16;
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break;
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case ATOMISP_INPUT_FORMAT_BINARY_8:
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*fmt_type = MIPI_FORMAT_BINARY_8;
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break;
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#else
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case ATOMISP_INPUT_FORMAT_USER_DEF1:
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*fmt_type = MIPI_FORMAT_CUSTOM0;
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break;
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case ATOMISP_INPUT_FORMAT_USER_DEF2:
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*fmt_type = MIPI_FORMAT_CUSTOM1;
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break;
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case ATOMISP_INPUT_FORMAT_USER_DEF3:
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*fmt_type = MIPI_FORMAT_CUSTOM2;
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break;
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case ATOMISP_INPUT_FORMAT_USER_DEF4:
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*fmt_type = MIPI_FORMAT_CUSTOM3;
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break;
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case ATOMISP_INPUT_FORMAT_USER_DEF5:
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*fmt_type = MIPI_FORMAT_CUSTOM4;
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break;
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case ATOMISP_INPUT_FORMAT_USER_DEF6:
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*fmt_type = MIPI_FORMAT_CUSTOM5;
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break;
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case ATOMISP_INPUT_FORMAT_USER_DEF7:
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*fmt_type = MIPI_FORMAT_CUSTOM6;
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break;
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case ATOMISP_INPUT_FORMAT_USER_DEF8:
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*fmt_type = MIPI_FORMAT_CUSTOM7;
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break;
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#endif
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case ATOMISP_INPUT_FORMAT_YUV420_16:
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case ATOMISP_INPUT_FORMAT_YUV422_16:
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default:
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return -EINVAL;
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}
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return 0;
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}
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#if defined(ISP2401)
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static mipi_predictor_t sh_css_csi2_compression_type_2_mipi_predictor(
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enum ia_css_csi2_compression_type type)
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{
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mipi_predictor_t predictor = MIPI_PREDICTOR_NONE;
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switch (type) {
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case IA_CSS_CSI2_COMPRESSION_TYPE_1:
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predictor = MIPI_PREDICTOR_TYPE1 - 1;
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break;
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case IA_CSS_CSI2_COMPRESSION_TYPE_2:
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predictor = MIPI_PREDICTOR_TYPE2 - 1;
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default:
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break;
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}
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return predictor;
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}
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int ia_css_isys_convert_compressed_format(
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struct ia_css_csi2_compression *comp,
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struct isp2401_input_system_cfg_s *cfg)
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{
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int err = 0;
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assert(comp);
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assert(cfg);
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if (comp->type != IA_CSS_CSI2_COMPRESSION_TYPE_NONE) {
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/* compression register bit slicing
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4 bit for each user defined data type
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3 bit indicate compression scheme
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000 No compression
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001 10-6-10
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010 10-7-10
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011 10-8-10
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100 12-6-12
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101 12-6-12
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100 12-7-12
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110 12-8-12
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1 bit indicate predictor
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*/
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if (comp->uncompressed_bits_per_pixel == UNCOMPRESSED_BITS_PER_PIXEL_10) {
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switch (comp->compressed_bits_per_pixel) {
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case COMPRESSED_BITS_PER_PIXEL_6:
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cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_6_10;
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break;
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case COMPRESSED_BITS_PER_PIXEL_7:
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cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_7_10;
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break;
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case COMPRESSED_BITS_PER_PIXEL_8:
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cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_8_10;
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break;
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default:
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err = -EINVAL;
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}
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} else if (comp->uncompressed_bits_per_pixel ==
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UNCOMPRESSED_BITS_PER_PIXEL_12) {
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switch (comp->compressed_bits_per_pixel) {
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case COMPRESSED_BITS_PER_PIXEL_6:
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cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_6_12;
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break;
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case COMPRESSED_BITS_PER_PIXEL_7:
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cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_7_12;
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break;
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case COMPRESSED_BITS_PER_PIXEL_8:
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cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_8_12;
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break;
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default:
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err = -EINVAL;
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}
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} else
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err = -EINVAL;
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cfg->csi_port_attr.comp_predictor =
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sh_css_csi2_compression_type_2_mipi_predictor(comp->type);
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cfg->csi_port_attr.comp_enable = true;
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} else /* No compression */
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cfg->csi_port_attr.comp_enable = false;
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return err;
|
}
|
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unsigned int ia_css_csi2_calculate_input_system_alignment(
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enum atomisp_input_format fmt_type)
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{
|
unsigned int memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES;
|
|
switch (fmt_type) {
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case ATOMISP_INPUT_FORMAT_RAW_6:
|
case ATOMISP_INPUT_FORMAT_RAW_7:
|
case ATOMISP_INPUT_FORMAT_RAW_8:
|
case ATOMISP_INPUT_FORMAT_RAW_10:
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case ATOMISP_INPUT_FORMAT_RAW_12:
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case ATOMISP_INPUT_FORMAT_RAW_14:
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memory_alignment_in_bytes = 2 * ISP_VEC_NELEMS;
|
break;
|
case ATOMISP_INPUT_FORMAT_YUV420_8:
|
case ATOMISP_INPUT_FORMAT_YUV422_8:
|
case ATOMISP_INPUT_FORMAT_USER_DEF1:
|
case ATOMISP_INPUT_FORMAT_USER_DEF2:
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case ATOMISP_INPUT_FORMAT_USER_DEF3:
|
case ATOMISP_INPUT_FORMAT_USER_DEF4:
|
case ATOMISP_INPUT_FORMAT_USER_DEF5:
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case ATOMISP_INPUT_FORMAT_USER_DEF6:
|
case ATOMISP_INPUT_FORMAT_USER_DEF7:
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case ATOMISP_INPUT_FORMAT_USER_DEF8:
|
/* Planar YUV formats need to have all planes aligned, this means
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* double the alignment for the Y plane if the horizontal decimation is 2. */
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memory_alignment_in_bytes = 2 * HIVE_ISP_DDR_WORD_BYTES;
|
break;
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case ATOMISP_INPUT_FORMAT_EMBEDDED:
|
default:
|
memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES;
|
break;
|
}
|
return memory_alignment_in_bytes;
|
}
|
|
#endif
|
|
#if !defined(ISP2401)
|
void ia_css_isys_rx_configure(const rx_cfg_t *config,
|
const enum ia_css_input_mode input_mode)
|
{
|
bool port_enabled[N_MIPI_PORT_ID];
|
bool any_port_enabled = false;
|
enum mipi_port_id port;
|
|
if ((!config)
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|| (config->mode >= N_RX_MODE)
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|| (config->port >= N_MIPI_PORT_ID)) {
|
assert(0);
|
return;
|
}
|
for (port = (enum mipi_port_id)0; port < N_MIPI_PORT_ID; port++) {
|
if (is_receiver_port_enabled(RX0_ID, port))
|
any_port_enabled = true;
|
}
|
/* AM: Check whether this is a problem with multiple
|
* streams. MS: This is the case. */
|
|
port = config->port;
|
receiver_port_enable(RX0_ID, port, false);
|
|
port = config->port;
|
|
/* AM: Check whether this is a problem with multiple streams. */
|
if (MIPI_PORT_LANES[config->mode][port] != MIPI_0LANE_CFG) {
|
receiver_port_reg_store(RX0_ID, port,
|
_HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX,
|
config->timeout);
|
receiver_port_reg_store(RX0_ID, port,
|
_HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX,
|
config->initcount);
|
receiver_port_reg_store(RX0_ID, port,
|
_HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX,
|
config->synccount);
|
receiver_port_reg_store(RX0_ID, port,
|
_HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX,
|
config->rxcount);
|
|
port_enabled[port] = true;
|
|
if (input_mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) {
|
/* MW: A bit of a hack, straight wiring of the capture
|
* units,assuming they are linearly enumerated. */
|
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
|
GPREGS_UNIT0_ID,
|
HIVE_ISYS_GPREG_MULTICAST_A_IDX
|
+ (unsigned int)port,
|
INPUT_SYSTEM_CSI_BACKEND);
|
/* MW: Like the integration test example we overwite,
|
* the GPREG_MUX register */
|
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
|
GPREGS_UNIT0_ID,
|
HIVE_ISYS_GPREG_MUX_IDX,
|
(input_system_multiplex_t)port);
|
} else {
|
/*
|
* AM: A bit of a hack, wiring the input system.
|
*/
|
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
|
GPREGS_UNIT0_ID,
|
HIVE_ISYS_GPREG_MULTICAST_A_IDX
|
+ (unsigned int)port,
|
INPUT_SYSTEM_INPUT_BUFFER);
|
input_system_sub_system_reg_store(INPUT_SYSTEM0_ID,
|
GPREGS_UNIT0_ID,
|
HIVE_ISYS_GPREG_MUX_IDX,
|
INPUT_SYSTEM_ACQUISITION_UNIT);
|
}
|
}
|
/*
|
* The 2ppc is shared for all ports, so we cannot
|
* disable->configure->enable individual ports
|
*/
|
/* AM: Check whether this is a problem with multiple streams. */
|
/* MS: 2ppc should be a property per binary and should be
|
* enabled/disabled per binary.
|
* Currently it is implemented as a system wide setting due
|
* to effort and risks. */
|
if (!any_port_enabled) {
|
receiver_reg_store(RX0_ID,
|
_HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX,
|
config->is_two_ppc);
|
receiver_reg_store(RX0_ID, _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX,
|
config->is_two_ppc);
|
}
|
receiver_port_enable(RX0_ID, port, true);
|
/* TODO: JB: need to add the beneath used define to mizuchi */
|
/* sh_css_sw_hive_isp_css_2400_system_20121224_0125\css
|
* \hrt\input_system_defs.h
|
* #define INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG 0X207
|
*/
|
/* TODO: need better name for define
|
* input_system_reg_store(INPUT_SYSTEM0_ID,
|
* INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG, 1);
|
*/
|
input_system_reg_store(INPUT_SYSTEM0_ID, 0x207, 1);
|
|
return;
|
}
|
|
void ia_css_isys_rx_disable(void)
|
{
|
enum mipi_port_id port;
|
|
for (port = (enum mipi_port_id)0; port < N_MIPI_PORT_ID; port++) {
|
receiver_port_reg_store(RX0_ID, port,
|
_HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX,
|
false);
|
}
|
return;
|
}
|
#endif /* if !defined(ISP2401) */
|
