// SPDX-License-Identifier: GPL-2.0+
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/*
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* KP2000 SPI controller driver
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*
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* Copyright (C) 2014-2018 Daktronics
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* Author: Matt Sickler <matt.sickler@daktronics.com>
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* Very loosely based on spi-omap2-mcspi.c
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/slab.h>
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#include <linux/pm_runtime.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/gcd.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/flash.h>
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#include <linux/mtd/partitions.h>
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#include "kpc.h"
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static struct mtd_partition p2kr0_spi0_parts[] = {
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{ .name = "SLOT_0", .size = 7798784, .offset = 0, },
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{ .name = "SLOT_1", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
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{ .name = "SLOT_2", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
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{ .name = "SLOT_3", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
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{ .name = "CS0_EXTRA", .size = MTDPART_SIZ_FULL, .offset = MTDPART_OFS_NXTBLK},
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};
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static struct mtd_partition p2kr0_spi1_parts[] = {
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{ .name = "SLOT_4", .size = 7798784, .offset = 0, },
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{ .name = "SLOT_5", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
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{ .name = "SLOT_6", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
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{ .name = "SLOT_7", .size = 7798784, .offset = MTDPART_OFS_NXTBLK},
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{ .name = "CS1_EXTRA", .size = MTDPART_SIZ_FULL, .offset = MTDPART_OFS_NXTBLK},
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};
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static struct flash_platform_data p2kr0_spi0_pdata = {
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.name = "SPI0",
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.nr_parts = ARRAY_SIZE(p2kr0_spi0_parts),
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.parts = p2kr0_spi0_parts,
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};
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static struct flash_platform_data p2kr0_spi1_pdata = {
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.name = "SPI1",
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.nr_parts = ARRAY_SIZE(p2kr0_spi1_parts),
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.parts = p2kr0_spi1_parts,
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};
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static struct spi_board_info p2kr0_board_info[] = {
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{
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.modalias = "n25q256a11",
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.bus_num = 1,
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.chip_select = 0,
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.mode = SPI_MODE_0,
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.platform_data = &p2kr0_spi0_pdata
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},
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{
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.modalias = "n25q256a11",
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.bus_num = 1,
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.chip_select = 1,
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.mode = SPI_MODE_0,
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.platform_data = &p2kr0_spi1_pdata
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},
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};
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/***************
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* SPI Defines *
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***************/
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#define KP_SPI_REG_CONFIG 0x0 /* 0x00 */
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#define KP_SPI_REG_STATUS 0x1 /* 0x08 */
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#define KP_SPI_REG_FFCTRL 0x2 /* 0x10 */
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#define KP_SPI_REG_TXDATA 0x3 /* 0x18 */
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#define KP_SPI_REG_RXDATA 0x4 /* 0x20 */
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#define KP_SPI_CLK 48000000
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#define KP_SPI_MAX_FIFODEPTH 64
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#define KP_SPI_MAX_FIFOWCNT 0xFFFF
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#define KP_SPI_REG_CONFIG_TRM_TXRX 0
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#define KP_SPI_REG_CONFIG_TRM_RX 1
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#define KP_SPI_REG_CONFIG_TRM_TX 2
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#define KP_SPI_REG_STATUS_RXS 0x01
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#define KP_SPI_REG_STATUS_TXS 0x02
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#define KP_SPI_REG_STATUS_EOT 0x04
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#define KP_SPI_REG_STATUS_TXFFE 0x10
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#define KP_SPI_REG_STATUS_TXFFF 0x20
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#define KP_SPI_REG_STATUS_RXFFE 0x40
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#define KP_SPI_REG_STATUS_RXFFF 0x80
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/******************
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* SPI Structures *
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******************/
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struct kp_spi {
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struct spi_master *master;
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u64 __iomem *base;
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struct device *dev;
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};
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struct kp_spi_controller_state {
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void __iomem *base;
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s64 conf_cache;
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};
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union kp_spi_config {
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/* use this to access individual elements */
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struct __packed spi_config_bitfield {
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unsigned int pha : 1; /* spim_clk Phase */
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unsigned int pol : 1; /* spim_clk Polarity */
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unsigned int epol : 1; /* spim_csx Polarity */
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unsigned int dpe : 1; /* Transmission Enable */
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unsigned int wl : 5; /* Word Length */
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unsigned int : 3;
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unsigned int trm : 2; /* TxRx Mode */
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unsigned int cs : 4; /* Chip Select */
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unsigned int wcnt : 7; /* Word Count */
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unsigned int ffen : 1; /* FIFO Enable */
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unsigned int spi_en : 1; /* SPI Enable */
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unsigned int : 5;
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} bitfield;
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/* use this to grab the whole register */
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u32 reg;
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};
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union kp_spi_status {
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struct __packed spi_status_bitfield {
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unsigned int rx : 1; /* Rx Status */
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unsigned int tx : 1; /* Tx Status */
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unsigned int eo : 1; /* End of Transfer */
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unsigned int : 1;
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unsigned int txffe : 1; /* Tx FIFO Empty */
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unsigned int txfff : 1; /* Tx FIFO Full */
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unsigned int rxffe : 1; /* Rx FIFO Empty */
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unsigned int rxfff : 1; /* Rx FIFO Full */
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unsigned int : 24;
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} bitfield;
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u32 reg;
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};
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union kp_spi_ffctrl {
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struct __packed spi_ffctrl_bitfield {
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unsigned int ffstart : 1; /* FIFO Start */
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unsigned int : 31;
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} bitfield;
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u32 reg;
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};
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/***************
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* SPI Helpers *
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***************/
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static inline u64
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kp_spi_read_reg(struct kp_spi_controller_state *cs, int idx)
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{
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u64 __iomem *addr = cs->base;
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addr += idx;
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if ((idx == KP_SPI_REG_CONFIG) && (cs->conf_cache >= 0))
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return cs->conf_cache;
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return readq(addr);
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}
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static inline void
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kp_spi_write_reg(struct kp_spi_controller_state *cs, int idx, u64 val)
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{
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u64 __iomem *addr = cs->base;
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addr += idx;
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writeq(val, addr);
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if (idx == KP_SPI_REG_CONFIG)
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cs->conf_cache = val;
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}
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static int
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kp_spi_wait_for_reg_bit(struct kp_spi_controller_state *cs, int idx,
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unsigned long bit)
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{
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unsigned long timeout;
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timeout = jiffies + msecs_to_jiffies(1000);
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while (!(kp_spi_read_reg(cs, idx) & bit)) {
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if (time_after(jiffies, timeout)) {
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if (!(kp_spi_read_reg(cs, idx) & bit))
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return -ETIMEDOUT;
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else
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return 0;
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}
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cpu_relax();
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}
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return 0;
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}
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static unsigned
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kp_spi_txrx_pio(struct spi_device *spidev, struct spi_transfer *transfer)
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{
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struct kp_spi_controller_state *cs = spidev->controller_state;
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unsigned int count = transfer->len;
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unsigned int c = count;
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int i;
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int res;
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u8 *rx = transfer->rx_buf;
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const u8 *tx = transfer->tx_buf;
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int processed = 0;
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if (tx) {
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for (i = 0 ; i < c ; i++) {
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char val = *tx++;
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res = kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
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KP_SPI_REG_STATUS_TXS);
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if (res < 0)
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goto out;
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kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, val);
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processed++;
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}
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} else if (rx) {
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for (i = 0 ; i < c ; i++) {
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char test = 0;
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kp_spi_write_reg(cs, KP_SPI_REG_TXDATA, 0x00);
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res = kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
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KP_SPI_REG_STATUS_RXS);
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if (res < 0)
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goto out;
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test = kp_spi_read_reg(cs, KP_SPI_REG_RXDATA);
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*rx++ = test;
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processed++;
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}
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}
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if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
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KP_SPI_REG_STATUS_EOT) < 0) {
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//TODO: Figure out how to abort transaction??
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//Ths has never happened in practice though...
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}
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out:
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return processed;
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}
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/*****************
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* SPI Functions *
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*****************/
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static int
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kp_spi_setup(struct spi_device *spidev)
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{
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union kp_spi_config sc;
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struct kp_spi *kpspi = spi_master_get_devdata(spidev->master);
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struct kp_spi_controller_state *cs;
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/* setup controller state */
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cs = spidev->controller_state;
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if (!cs) {
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cs = kzalloc(sizeof(*cs), GFP_KERNEL);
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if (!cs)
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return -ENOMEM;
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cs->base = kpspi->base;
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cs->conf_cache = -1;
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spidev->controller_state = cs;
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}
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/* set config register */
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sc.bitfield.wl = spidev->bits_per_word - 1;
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sc.bitfield.cs = spidev->chip_select;
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sc.bitfield.spi_en = 0;
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sc.bitfield.trm = 0;
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sc.bitfield.ffen = 0;
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kp_spi_write_reg(spidev->controller_state, KP_SPI_REG_CONFIG, sc.reg);
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return 0;
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}
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static int
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kp_spi_transfer_one_message(struct spi_master *master, struct spi_message *m)
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{
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struct kp_spi_controller_state *cs;
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struct spi_device *spidev;
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struct kp_spi *kpspi;
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struct spi_transfer *transfer;
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union kp_spi_config sc;
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int status = 0;
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spidev = m->spi;
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kpspi = spi_master_get_devdata(master);
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m->actual_length = 0;
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m->status = 0;
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cs = spidev->controller_state;
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/* reject invalid messages and transfers */
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if (list_empty(&m->transfers))
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return -EINVAL;
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/* validate input */
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list_for_each_entry(transfer, &m->transfers, transfer_list) {
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const void *tx_buf = transfer->tx_buf;
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void *rx_buf = transfer->rx_buf;
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unsigned int len = transfer->len;
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if (transfer->speed_hz > KP_SPI_CLK ||
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(len && !(rx_buf || tx_buf))) {
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dev_dbg(kpspi->dev, " transfer: %d Hz, %d %s%s, %d bpw\n",
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transfer->speed_hz,
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len,
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tx_buf ? "tx" : "",
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rx_buf ? "rx" : "",
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transfer->bits_per_word);
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dev_dbg(kpspi->dev, " transfer -EINVAL\n");
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return -EINVAL;
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}
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if (transfer->speed_hz &&
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transfer->speed_hz < (KP_SPI_CLK >> 15)) {
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dev_dbg(kpspi->dev, "speed_hz %d below minimum %d Hz\n",
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transfer->speed_hz,
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KP_SPI_CLK >> 15);
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dev_dbg(kpspi->dev, " speed_hz -EINVAL\n");
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return -EINVAL;
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}
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}
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/* assert chip select to start the sequence*/
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sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
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sc.bitfield.spi_en = 1;
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kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
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/* work */
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if (kp_spi_wait_for_reg_bit(cs, KP_SPI_REG_STATUS,
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KP_SPI_REG_STATUS_EOT) < 0) {
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dev_info(kpspi->dev, "EOT timed out\n");
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goto out;
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}
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/* do the transfers for this message */
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list_for_each_entry(transfer, &m->transfers, transfer_list) {
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if (!transfer->tx_buf && !transfer->rx_buf &&
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transfer->len) {
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status = -EINVAL;
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goto error;
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}
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/* transfer */
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if (transfer->len) {
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unsigned int word_len = spidev->bits_per_word;
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unsigned int count;
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/* set up the transfer... */
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sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
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/* ...direction */
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if (transfer->tx_buf)
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sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_TX;
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else if (transfer->rx_buf)
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sc.bitfield.trm = KP_SPI_REG_CONFIG_TRM_RX;
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/* ...word length */
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if (transfer->bits_per_word)
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word_len = transfer->bits_per_word;
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sc.bitfield.wl = word_len - 1;
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/* ...chip select */
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sc.bitfield.cs = spidev->chip_select;
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/* ...and write the new settings */
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kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
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/* do the transfer */
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count = kp_spi_txrx_pio(spidev, transfer);
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m->actual_length += count;
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if (count != transfer->len) {
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status = -EIO;
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goto error;
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}
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}
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if (transfer->delay.value)
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ndelay(spi_delay_to_ns(&transfer->delay, transfer));
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}
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/* de-assert chip select to end the sequence */
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sc.reg = kp_spi_read_reg(cs, KP_SPI_REG_CONFIG);
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sc.bitfield.spi_en = 0;
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kp_spi_write_reg(cs, KP_SPI_REG_CONFIG, sc.reg);
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out:
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/* done work */
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spi_finalize_current_message(master);
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return 0;
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error:
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m->status = status;
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return status;
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}
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static void
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kp_spi_cleanup(struct spi_device *spidev)
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{
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struct kp_spi_controller_state *cs = spidev->controller_state;
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kfree(cs);
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}
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/******************
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* Probe / Remove *
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******************/
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static int
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kp_spi_probe(struct platform_device *pldev)
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{
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struct kpc_core_device_platdata *drvdata;
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struct spi_master *master;
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struct kp_spi *kpspi;
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struct resource *r;
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int status = 0;
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int i;
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drvdata = pldev->dev.platform_data;
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if (!drvdata) {
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dev_err(&pldev->dev, "%s: platform_data is NULL\n", __func__);
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return -ENODEV;
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}
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master = spi_alloc_master(&pldev->dev, sizeof(struct kp_spi));
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if (!master) {
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dev_err(&pldev->dev, "%s: master allocation failed\n",
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__func__);
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return -ENOMEM;
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}
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/* set up the spi functions */
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
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master->bits_per_word_mask = (unsigned int)SPI_BPW_RANGE_MASK(4, 32);
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master->setup = kp_spi_setup;
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master->transfer_one_message = kp_spi_transfer_one_message;
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master->cleanup = kp_spi_cleanup;
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platform_set_drvdata(pldev, master);
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kpspi = spi_master_get_devdata(master);
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kpspi->master = master;
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kpspi->dev = &pldev->dev;
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master->num_chipselect = 4;
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if (pldev->id != -1)
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master->bus_num = pldev->id;
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r = platform_get_resource(pldev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pldev->dev, "%s: Unable to get platform resources\n",
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__func__);
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status = -ENODEV;
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goto free_master;
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}
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kpspi->base = devm_ioremap(&pldev->dev, r->start,
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resource_size(r));
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status = spi_register_master(master);
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if (status < 0) {
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dev_err(&pldev->dev, "Unable to register SPI device\n");
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goto free_master;
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}
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/* register the slave boards */
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#define NEW_SPI_DEVICE_FROM_BOARD_INFO_TABLE(table) \
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for (i = 0 ; i < ARRAY_SIZE(table) ; i++) { \
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spi_new_device(master, &table[i]); \
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}
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switch ((drvdata->card_id & 0xFFFF0000) >> 16) {
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case PCI_DEVICE_ID_DAKTRONICS_KADOKA_P2KR0:
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NEW_SPI_DEVICE_FROM_BOARD_INFO_TABLE(p2kr0_board_info);
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break;
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default:
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dev_err(&pldev->dev, "Unknown hardware, cant know what partition table to use!\n");
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goto free_master;
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}
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return status;
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free_master:
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spi_master_put(master);
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return status;
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}
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static int
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kp_spi_remove(struct platform_device *pldev)
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{
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struct spi_master *master = platform_get_drvdata(pldev);
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spi_unregister_master(master);
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return 0;
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}
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static struct platform_driver kp_spi_driver = {
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.driver = {
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.name = KP_DRIVER_NAME_SPI,
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},
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.probe = kp_spi_probe,
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.remove = kp_spi_remove,
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};
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module_platform_driver(kp_spi_driver);
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:kp_spi");
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