// SPDX-License-Identifier: GPL-2.0
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/*
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* AD9833/AD9834/AD9837/AD9838 SPI DDS driver
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*
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* Copyright 2010-2011 Analog Devices Inc.
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*/
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#include <linux/clk.h>
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#include <linux/interrupt.h>
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#include <linux/workqueue.h>
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#include <linux/device.h>
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#include <linux/kernel.h>
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#include <linux/slab.h>
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#include <linux/sysfs.h>
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#include <linux/list.h>
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#include <linux/spi/spi.h>
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#include <linux/regulator/consumer.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <asm/div64.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include "dds.h"
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#include "ad9834.h"
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/* Registers */
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#define AD9834_REG_CMD 0
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#define AD9834_REG_FREQ0 BIT(14)
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#define AD9834_REG_FREQ1 BIT(15)
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#define AD9834_REG_PHASE0 (BIT(15) | BIT(14))
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#define AD9834_REG_PHASE1 (BIT(15) | BIT(14) | BIT(13))
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/* Command Control Bits */
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#define AD9834_B28 BIT(13)
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#define AD9834_HLB BIT(12)
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#define AD9834_FSEL BIT(11)
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#define AD9834_PSEL BIT(10)
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#define AD9834_PIN_SW BIT(9)
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#define AD9834_RESET BIT(8)
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#define AD9834_SLEEP1 BIT(7)
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#define AD9834_SLEEP12 BIT(6)
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#define AD9834_OPBITEN BIT(5)
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#define AD9834_SIGN_PIB BIT(4)
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#define AD9834_DIV2 BIT(3)
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#define AD9834_MODE BIT(1)
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#define AD9834_FREQ_BITS 28
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#define AD9834_PHASE_BITS 12
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#define RES_MASK(bits) (BIT(bits) - 1)
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/**
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* struct ad9834_state - driver instance specific data
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* @spi: spi_device
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* @reg: supply regulator
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* @mclk: external master clock
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* @control: cached control word
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* @xfer: default spi transfer
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* @msg: default spi message
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* @freq_xfer: tuning word spi transfer
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* @freq_msg: tuning word spi message
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* @lock: protect sensor state
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* @data: spi transmit buffer
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* @freq_data: tuning word spi transmit buffer
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*/
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struct ad9834_state {
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struct spi_device *spi;
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struct regulator *reg;
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struct clk *mclk;
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unsigned short control;
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unsigned short devid;
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struct spi_transfer xfer;
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struct spi_message msg;
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struct spi_transfer freq_xfer[2];
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struct spi_message freq_msg;
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struct mutex lock; /* protect sensor state */
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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__be16 data ____cacheline_aligned;
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__be16 freq_data[2];
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};
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/**
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* ad9834_supported_device_ids:
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*/
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enum ad9834_supported_device_ids {
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ID_AD9833,
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ID_AD9834,
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ID_AD9837,
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ID_AD9838,
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};
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static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout)
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{
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unsigned long long freqreg = (u64)fout * (u64)BIT(AD9834_FREQ_BITS);
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do_div(freqreg, mclk);
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return freqreg;
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}
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static int ad9834_write_frequency(struct ad9834_state *st,
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unsigned long addr, unsigned long fout)
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{
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unsigned long clk_freq;
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unsigned long regval;
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clk_freq = clk_get_rate(st->mclk);
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if (fout > (clk_freq / 2))
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return -EINVAL;
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regval = ad9834_calc_freqreg(clk_freq, fout);
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st->freq_data[0] = cpu_to_be16(addr | (regval &
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RES_MASK(AD9834_FREQ_BITS / 2)));
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st->freq_data[1] = cpu_to_be16(addr | ((regval >>
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(AD9834_FREQ_BITS / 2)) &
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RES_MASK(AD9834_FREQ_BITS / 2)));
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return spi_sync(st->spi, &st->freq_msg);
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}
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static int ad9834_write_phase(struct ad9834_state *st,
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unsigned long addr, unsigned long phase)
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{
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if (phase > BIT(AD9834_PHASE_BITS))
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return -EINVAL;
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st->data = cpu_to_be16(addr | phase);
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return spi_sync(st->spi, &st->msg);
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}
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static ssize_t ad9834_write(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t len)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad9834_state *st = iio_priv(indio_dev);
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struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
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int ret;
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unsigned long val;
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ret = kstrtoul(buf, 10, &val);
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if (ret)
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return ret;
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mutex_lock(&st->lock);
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switch ((u32)this_attr->address) {
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case AD9834_REG_FREQ0:
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case AD9834_REG_FREQ1:
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ret = ad9834_write_frequency(st, this_attr->address, val);
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break;
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case AD9834_REG_PHASE0:
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case AD9834_REG_PHASE1:
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ret = ad9834_write_phase(st, this_attr->address, val);
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break;
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case AD9834_OPBITEN:
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if (st->control & AD9834_MODE) {
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ret = -EINVAL; /* AD9843 reserved mode */
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break;
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}
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if (val)
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st->control |= AD9834_OPBITEN;
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else
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st->control &= ~AD9834_OPBITEN;
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st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
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ret = spi_sync(st->spi, &st->msg);
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break;
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case AD9834_PIN_SW:
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if (val)
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st->control |= AD9834_PIN_SW;
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else
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st->control &= ~AD9834_PIN_SW;
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st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
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ret = spi_sync(st->spi, &st->msg);
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break;
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case AD9834_FSEL:
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case AD9834_PSEL:
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if (!val) {
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st->control &= ~(this_attr->address | AD9834_PIN_SW);
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} else if (val == 1) {
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st->control |= this_attr->address;
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st->control &= ~AD9834_PIN_SW;
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} else {
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ret = -EINVAL;
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break;
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}
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st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
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ret = spi_sync(st->spi, &st->msg);
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break;
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case AD9834_RESET:
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if (val)
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st->control &= ~AD9834_RESET;
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else
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st->control |= AD9834_RESET;
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st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
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ret = spi_sync(st->spi, &st->msg);
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break;
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default:
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ret = -ENODEV;
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}
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mutex_unlock(&st->lock);
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return ret ? ret : len;
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}
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static ssize_t ad9834_store_wavetype(struct device *dev,
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struct device_attribute *attr,
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const char *buf,
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size_t len)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad9834_state *st = iio_priv(indio_dev);
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struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
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int ret = 0;
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bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
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mutex_lock(&st->lock);
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switch ((u32)this_attr->address) {
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case 0:
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if (sysfs_streq(buf, "sine")) {
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st->control &= ~AD9834_MODE;
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if (is_ad9833_7)
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st->control &= ~AD9834_OPBITEN;
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} else if (sysfs_streq(buf, "triangle")) {
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if (is_ad9833_7) {
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st->control &= ~AD9834_OPBITEN;
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st->control |= AD9834_MODE;
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} else if (st->control & AD9834_OPBITEN) {
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ret = -EINVAL; /* AD9843 reserved mode */
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} else {
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st->control |= AD9834_MODE;
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}
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} else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
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st->control &= ~AD9834_MODE;
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st->control |= AD9834_OPBITEN;
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} else {
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ret = -EINVAL;
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}
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break;
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case 1:
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if (sysfs_streq(buf, "square") &&
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!(st->control & AD9834_MODE)) {
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st->control &= ~AD9834_MODE;
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st->control |= AD9834_OPBITEN;
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} else {
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ret = -EINVAL;
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}
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break;
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default:
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ret = -EINVAL;
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break;
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}
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if (!ret) {
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st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
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ret = spi_sync(st->spi, &st->msg);
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}
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mutex_unlock(&st->lock);
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return ret ? ret : len;
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}
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static
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ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad9834_state *st = iio_priv(indio_dev);
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char *str;
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if (st->devid == ID_AD9833 || st->devid == ID_AD9837)
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str = "sine triangle square";
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else if (st->control & AD9834_OPBITEN)
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str = "sine";
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else
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str = "sine triangle";
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return sprintf(buf, "%s\n", str);
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}
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static IIO_DEVICE_ATTR(out_altvoltage0_out0_wavetype_available, 0444,
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ad9834_show_out0_wavetype_available, NULL, 0);
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static
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ssize_t ad9834_show_out1_wavetype_available(struct device *dev,
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struct device_attribute *attr,
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char *buf)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad9834_state *st = iio_priv(indio_dev);
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char *str;
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if (st->control & AD9834_MODE)
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str = "";
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else
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str = "square";
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return sprintf(buf, "%s\n", str);
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}
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static IIO_DEVICE_ATTR(out_altvoltage0_out1_wavetype_available, 0444,
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ad9834_show_out1_wavetype_available, NULL, 0);
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/**
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* see dds.h for further information
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*/
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static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9834_write, AD9834_REG_FREQ0);
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static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9834_write, AD9834_REG_FREQ1);
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static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9834_write, AD9834_FSEL);
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static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
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static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9834_write, AD9834_REG_PHASE0);
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static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9834_write, AD9834_REG_PHASE1);
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static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL, ad9834_write, AD9834_PSEL);
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static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
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static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
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ad9834_write, AD9834_PIN_SW);
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static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL, ad9834_write, AD9834_RESET);
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static IIO_DEV_ATTR_OUTY_ENABLE(0, 1, 0200, NULL,
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ad9834_write, AD9834_OPBITEN);
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static IIO_DEV_ATTR_OUT_WAVETYPE(0, 0, ad9834_store_wavetype, 0);
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static IIO_DEV_ATTR_OUT_WAVETYPE(0, 1, ad9834_store_wavetype, 1);
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static struct attribute *ad9834_attributes[] = {
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&iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
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&iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
|
&iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
|
&iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_out1_enable.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
|
&iio_dev_attr_out_altvoltage0_out1_wavetype.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_out1_wavetype_available.dev_attr.attr,
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NULL,
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};
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static struct attribute *ad9833_attributes[] = {
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&iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
|
&iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
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&iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
|
&iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
|
&iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_out0_wavetype.dev_attr.attr,
|
&iio_dev_attr_out_altvoltage0_out0_wavetype_available.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group ad9834_attribute_group = {
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.attrs = ad9834_attributes,
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};
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static const struct attribute_group ad9833_attribute_group = {
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.attrs = ad9833_attributes,
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};
|
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static const struct iio_info ad9834_info = {
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.attrs = &ad9834_attribute_group,
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};
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static const struct iio_info ad9833_info = {
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.attrs = &ad9833_attribute_group,
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};
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static int ad9834_probe(struct spi_device *spi)
|
{
|
struct ad9834_state *st;
|
struct iio_dev *indio_dev;
|
struct regulator *reg;
|
int ret;
|
|
reg = devm_regulator_get(&spi->dev, "avdd");
|
if (IS_ERR(reg))
|
return PTR_ERR(reg);
|
|
ret = regulator_enable(reg);
|
if (ret) {
|
dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
|
return ret;
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}
|
|
indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
|
if (!indio_dev) {
|
ret = -ENOMEM;
|
goto error_disable_reg;
|
}
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spi_set_drvdata(spi, indio_dev);
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st = iio_priv(indio_dev);
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mutex_init(&st->lock);
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st->mclk = devm_clk_get(&spi->dev, NULL);
|
if (IS_ERR(st->mclk)) {
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ret = PTR_ERR(st->mclk);
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goto error_disable_reg;
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}
|
|
ret = clk_prepare_enable(st->mclk);
|
if (ret) {
|
dev_err(&spi->dev, "Failed to enable master clock\n");
|
goto error_disable_reg;
|
}
|
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st->spi = spi;
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st->devid = spi_get_device_id(spi)->driver_data;
|
st->reg = reg;
|
indio_dev->name = spi_get_device_id(spi)->name;
|
switch (st->devid) {
|
case ID_AD9833:
|
case ID_AD9837:
|
indio_dev->info = &ad9833_info;
|
break;
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default:
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indio_dev->info = &ad9834_info;
|
break;
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}
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indio_dev->modes = INDIO_DIRECT_MODE;
|
|
/* Setup default messages */
|
|
st->xfer.tx_buf = &st->data;
|
st->xfer.len = 2;
|
|
spi_message_init(&st->msg);
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spi_message_add_tail(&st->xfer, &st->msg);
|
|
st->freq_xfer[0].tx_buf = &st->freq_data[0];
|
st->freq_xfer[0].len = 2;
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st->freq_xfer[0].cs_change = 1;
|
st->freq_xfer[1].tx_buf = &st->freq_data[1];
|
st->freq_xfer[1].len = 2;
|
|
spi_message_init(&st->freq_msg);
|
spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
|
spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
|
|
st->control = AD9834_B28 | AD9834_RESET;
|
st->control |= AD9834_DIV2;
|
|
if (st->devid == ID_AD9834)
|
st->control |= AD9834_SIGN_PIB;
|
|
st->data = cpu_to_be16(AD9834_REG_CMD | st->control);
|
ret = spi_sync(st->spi, &st->msg);
|
if (ret) {
|
dev_err(&spi->dev, "device init failed\n");
|
goto error_clock_unprepare;
|
}
|
|
ret = ad9834_write_frequency(st, AD9834_REG_FREQ0, 1000000);
|
if (ret)
|
goto error_clock_unprepare;
|
|
ret = ad9834_write_frequency(st, AD9834_REG_FREQ1, 5000000);
|
if (ret)
|
goto error_clock_unprepare;
|
|
ret = ad9834_write_phase(st, AD9834_REG_PHASE0, 512);
|
if (ret)
|
goto error_clock_unprepare;
|
|
ret = ad9834_write_phase(st, AD9834_REG_PHASE1, 1024);
|
if (ret)
|
goto error_clock_unprepare;
|
|
ret = iio_device_register(indio_dev);
|
if (ret)
|
goto error_clock_unprepare;
|
|
return 0;
|
error_clock_unprepare:
|
clk_disable_unprepare(st->mclk);
|
error_disable_reg:
|
regulator_disable(reg);
|
|
return ret;
|
}
|
|
static int ad9834_remove(struct spi_device *spi)
|
{
|
struct iio_dev *indio_dev = spi_get_drvdata(spi);
|
struct ad9834_state *st = iio_priv(indio_dev);
|
|
iio_device_unregister(indio_dev);
|
clk_disable_unprepare(st->mclk);
|
regulator_disable(st->reg);
|
|
return 0;
|
}
|
|
static const struct spi_device_id ad9834_id[] = {
|
{"ad9833", ID_AD9833},
|
{"ad9834", ID_AD9834},
|
{"ad9837", ID_AD9837},
|
{"ad9838", ID_AD9838},
|
{}
|
};
|
MODULE_DEVICE_TABLE(spi, ad9834_id);
|
|
static const struct of_device_id ad9834_of_match[] = {
|
{.compatible = "adi,ad9833"},
|
{.compatible = "adi,ad9834"},
|
{.compatible = "adi,ad9837"},
|
{.compatible = "adi,ad9838"},
|
{}
|
};
|
|
MODULE_DEVICE_TABLE(of, ad9834_of_match);
|
|
static struct spi_driver ad9834_driver = {
|
.driver = {
|
.name = "ad9834",
|
.of_match_table = ad9834_of_match
|
},
|
.probe = ad9834_probe,
|
.remove = ad9834_remove,
|
.id_table = ad9834_id,
|
};
|
module_spi_driver(ad9834_driver);
|
|
MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
|
MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
|
MODULE_LICENSE("GPL v2");
|
