// SPDX-License-Identifier: GPL-2.0
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/*
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* AD9832 SPI DDS driver
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*
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* Copyright 2011 Analog Devices Inc.
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*/
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#include <asm/div64.h>
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#include <linux/clk.h>
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#include <linux/device.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/sysfs.h>
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#include <linux/iio/iio.h>
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#include <linux/iio/sysfs.h>
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#include "ad9832.h"
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#include "dds.h"
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/* Registers */
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#define AD9832_FREQ0LL 0x0
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#define AD9832_FREQ0HL 0x1
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#define AD9832_FREQ0LM 0x2
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#define AD9832_FREQ0HM 0x3
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#define AD9832_FREQ1LL 0x4
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#define AD9832_FREQ1HL 0x5
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#define AD9832_FREQ1LM 0x6
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#define AD9832_FREQ1HM 0x7
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#define AD9832_PHASE0L 0x8
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#define AD9832_PHASE0H 0x9
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#define AD9832_PHASE1L 0xA
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#define AD9832_PHASE1H 0xB
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#define AD9832_PHASE2L 0xC
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#define AD9832_PHASE2H 0xD
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#define AD9832_PHASE3L 0xE
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#define AD9832_PHASE3H 0xF
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#define AD9832_PHASE_SYM 0x10
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#define AD9832_FREQ_SYM 0x11
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#define AD9832_PINCTRL_EN 0x12
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#define AD9832_OUTPUT_EN 0x13
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/* Command Control Bits */
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#define AD9832_CMD_PHA8BITSW 0x1
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#define AD9832_CMD_PHA16BITSW 0x0
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#define AD9832_CMD_FRE8BITSW 0x3
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#define AD9832_CMD_FRE16BITSW 0x2
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#define AD9832_CMD_FPSELECT 0x6
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#define AD9832_CMD_SYNCSELSRC 0x8
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#define AD9832_CMD_SLEEPRESCLR 0xC
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#define AD9832_FREQ BIT(11)
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#define AD9832_PHASE(x) (((x) & 3) << 9)
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#define AD9832_SYNC BIT(13)
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#define AD9832_SELSRC BIT(12)
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#define AD9832_SLEEP BIT(13)
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#define AD9832_RESET BIT(12)
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#define AD9832_CLR BIT(11)
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#define CMD_SHIFT 12
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#define ADD_SHIFT 8
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#define AD9832_FREQ_BITS 32
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#define AD9832_PHASE_BITS 12
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#define RES_MASK(bits) ((1 << (bits)) - 1)
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/**
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* struct ad9832_state - driver instance specific data
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* @spi: spi_device
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* @avdd: supply regulator for the analog section
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* @dvdd: supply regulator for the digital section
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* @mclk: external master clock
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* @ctrl_fp: cached frequency/phase control word
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* @ctrl_ss: cached sync/selsrc control word
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* @ctrl_src: cached sleep/reset/clr word
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* @xfer: default spi transfer
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* @msg: default spi message
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* @freq_xfer: tuning word spi transfer
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* @freq_msg: tuning word spi message
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* @phase_xfer: tuning word spi transfer
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* @phase_msg: tuning word spi message
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* @lock protect sensor state
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* @data: spi transmit buffer
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* @phase_data: tuning word spi transmit buffer
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* @freq_data: tuning word spi transmit buffer
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*/
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struct ad9832_state {
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struct spi_device *spi;
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struct regulator *avdd;
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struct regulator *dvdd;
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struct clk *mclk;
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unsigned short ctrl_fp;
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unsigned short ctrl_ss;
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unsigned short ctrl_src;
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struct spi_transfer xfer;
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struct spi_message msg;
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struct spi_transfer freq_xfer[4];
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struct spi_message freq_msg;
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struct spi_transfer phase_xfer[2];
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struct spi_message phase_msg;
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struct mutex lock; /* protect sensor state */
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/*
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* DMA (thus cache coherency maintenance) requires the
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* transfer buffers to live in their own cache lines.
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*/
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union {
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__be16 freq_data[4]____cacheline_aligned;
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__be16 phase_data[2];
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__be16 data;
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};
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};
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static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
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{
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unsigned long long freqreg = (u64)fout *
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(u64)((u64)1L << AD9832_FREQ_BITS);
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do_div(freqreg, mclk);
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return freqreg;
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}
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static int ad9832_write_frequency(struct ad9832_state *st,
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unsigned int addr, unsigned long fout)
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{
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unsigned long regval;
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if (fout > (clk_get_rate(st->mclk) / 2))
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return -EINVAL;
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regval = ad9832_calc_freqreg(clk_get_rate(st->mclk), fout);
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st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
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(addr << ADD_SHIFT) |
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((regval >> 24) & 0xFF));
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st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
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((addr - 1) << ADD_SHIFT) |
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((regval >> 16) & 0xFF));
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st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
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((addr - 2) << ADD_SHIFT) |
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((regval >> 8) & 0xFF));
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st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
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((addr - 3) << ADD_SHIFT) |
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((regval >> 0) & 0xFF));
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return spi_sync(st->spi, &st->freq_msg);
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}
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static int ad9832_write_phase(struct ad9832_state *st,
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unsigned long addr, unsigned long phase)
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{
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if (phase > BIT(AD9832_PHASE_BITS))
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return -EINVAL;
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st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
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(addr << ADD_SHIFT) |
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((phase >> 8) & 0xFF));
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st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
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((addr - 1) << ADD_SHIFT) |
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(phase & 0xFF));
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return spi_sync(st->spi, &st->phase_msg);
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}
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static ssize_t ad9832_write(struct device *dev, struct device_attribute *attr,
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const char *buf, size_t len)
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{
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struct iio_dev *indio_dev = dev_to_iio_dev(dev);
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struct ad9832_state *st = iio_priv(indio_dev);
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struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
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int ret;
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unsigned long val;
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ret = kstrtoul(buf, 10, &val);
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if (ret)
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goto error_ret;
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mutex_lock(&st->lock);
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switch ((u32)this_attr->address) {
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case AD9832_FREQ0HM:
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case AD9832_FREQ1HM:
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ret = ad9832_write_frequency(st, this_attr->address, val);
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break;
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case AD9832_PHASE0H:
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case AD9832_PHASE1H:
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case AD9832_PHASE2H:
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case AD9832_PHASE3H:
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ret = ad9832_write_phase(st, this_attr->address, val);
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break;
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case AD9832_PINCTRL_EN:
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if (val)
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st->ctrl_ss &= ~AD9832_SELSRC;
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else
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st->ctrl_ss |= AD9832_SELSRC;
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st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
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st->ctrl_ss);
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ret = spi_sync(st->spi, &st->msg);
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break;
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case AD9832_FREQ_SYM:
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if (val == 1) {
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st->ctrl_fp |= AD9832_FREQ;
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} else if (val == 0) {
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st->ctrl_fp &= ~AD9832_FREQ;
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} else {
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ret = -EINVAL;
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break;
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}
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st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
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st->ctrl_fp);
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ret = spi_sync(st->spi, &st->msg);
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break;
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case AD9832_PHASE_SYM:
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if (val > 3) {
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ret = -EINVAL;
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break;
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}
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st->ctrl_fp &= ~AD9832_PHASE(3);
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st->ctrl_fp |= AD9832_PHASE(val);
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st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
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st->ctrl_fp);
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ret = spi_sync(st->spi, &st->msg);
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break;
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case AD9832_OUTPUT_EN:
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if (val)
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st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
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AD9832_CLR);
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else
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st->ctrl_src |= AD9832_RESET;
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st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
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st->ctrl_src);
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ret = spi_sync(st->spi, &st->msg);
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break;
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default:
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ret = -ENODEV;
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}
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mutex_unlock(&st->lock);
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error_ret:
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return ret ? ret : len;
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}
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/**
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* see dds.h for further information
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*/
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static IIO_DEV_ATTR_FREQ(0, 0, 0200, NULL, ad9832_write, AD9832_FREQ0HM);
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static IIO_DEV_ATTR_FREQ(0, 1, 0200, NULL, ad9832_write, AD9832_FREQ1HM);
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static IIO_DEV_ATTR_FREQSYMBOL(0, 0200, NULL, ad9832_write, AD9832_FREQ_SYM);
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static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
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static IIO_DEV_ATTR_PHASE(0, 0, 0200, NULL, ad9832_write, AD9832_PHASE0H);
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static IIO_DEV_ATTR_PHASE(0, 1, 0200, NULL, ad9832_write, AD9832_PHASE1H);
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static IIO_DEV_ATTR_PHASE(0, 2, 0200, NULL, ad9832_write, AD9832_PHASE2H);
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static IIO_DEV_ATTR_PHASE(0, 3, 0200, NULL, ad9832_write, AD9832_PHASE3H);
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static IIO_DEV_ATTR_PHASESYMBOL(0, 0200, NULL,
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ad9832_write, AD9832_PHASE_SYM);
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static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
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static IIO_DEV_ATTR_PINCONTROL_EN(0, 0200, NULL,
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ad9832_write, AD9832_PINCTRL_EN);
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static IIO_DEV_ATTR_OUT_ENABLE(0, 0200, NULL,
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ad9832_write, AD9832_OUTPUT_EN);
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static struct attribute *ad9832_attributes[] = {
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&iio_dev_attr_out_altvoltage0_frequency0.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_frequency1.dev_attr.attr,
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&iio_const_attr_out_altvoltage0_frequency_scale.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phase0.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phase1.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phase2.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phase3.dev_attr.attr,
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&iio_const_attr_out_altvoltage0_phase_scale.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_pincontrol_en.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_frequencysymbol.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_phasesymbol.dev_attr.attr,
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&iio_dev_attr_out_altvoltage0_out_enable.dev_attr.attr,
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NULL,
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};
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static const struct attribute_group ad9832_attribute_group = {
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.attrs = ad9832_attributes,
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};
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static const struct iio_info ad9832_info = {
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.attrs = &ad9832_attribute_group,
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};
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static int ad9832_probe(struct spi_device *spi)
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{
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struct ad9832_platform_data *pdata = dev_get_platdata(&spi->dev);
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struct iio_dev *indio_dev;
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struct ad9832_state *st;
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int ret;
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if (!pdata) {
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dev_dbg(&spi->dev, "no platform data?\n");
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return -ENODEV;
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}
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indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
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if (!indio_dev)
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return -ENOMEM;
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spi_set_drvdata(spi, indio_dev);
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st = iio_priv(indio_dev);
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st->avdd = devm_regulator_get(&spi->dev, "avdd");
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if (IS_ERR(st->avdd))
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return PTR_ERR(st->avdd);
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ret = regulator_enable(st->avdd);
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if (ret) {
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dev_err(&spi->dev, "Failed to enable specified AVDD supply\n");
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return ret;
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}
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st->dvdd = devm_regulator_get(&spi->dev, "dvdd");
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if (IS_ERR(st->dvdd)) {
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ret = PTR_ERR(st->dvdd);
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goto error_disable_avdd;
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}
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ret = regulator_enable(st->dvdd);
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if (ret) {
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dev_err(&spi->dev, "Failed to enable specified DVDD supply\n");
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goto error_disable_avdd;
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}
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st->mclk = devm_clk_get(&spi->dev, "mclk");
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if (IS_ERR(st->mclk)) {
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ret = PTR_ERR(st->mclk);
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goto error_disable_dvdd;
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}
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ret = clk_prepare_enable(st->mclk);
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if (ret < 0)
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goto error_disable_dvdd;
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st->spi = spi;
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mutex_init(&st->lock);
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indio_dev->name = spi_get_device_id(spi)->name;
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indio_dev->info = &ad9832_info;
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indio_dev->modes = INDIO_DIRECT_MODE;
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/* Setup default messages */
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st->xfer.tx_buf = &st->data;
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st->xfer.len = 2;
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spi_message_init(&st->msg);
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spi_message_add_tail(&st->xfer, &st->msg);
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st->freq_xfer[0].tx_buf = &st->freq_data[0];
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st->freq_xfer[0].len = 2;
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st->freq_xfer[0].cs_change = 1;
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st->freq_xfer[1].tx_buf = &st->freq_data[1];
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st->freq_xfer[1].len = 2;
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st->freq_xfer[1].cs_change = 1;
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st->freq_xfer[2].tx_buf = &st->freq_data[2];
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st->freq_xfer[2].len = 2;
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st->freq_xfer[2].cs_change = 1;
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st->freq_xfer[3].tx_buf = &st->freq_data[3];
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st->freq_xfer[3].len = 2;
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spi_message_init(&st->freq_msg);
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spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
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spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
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spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
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spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
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st->phase_xfer[0].tx_buf = &st->phase_data[0];
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st->phase_xfer[0].len = 2;
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st->phase_xfer[0].cs_change = 1;
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st->phase_xfer[1].tx_buf = &st->phase_data[1];
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st->phase_xfer[1].len = 2;
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spi_message_init(&st->phase_msg);
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spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
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spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
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st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
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st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
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st->ctrl_src);
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ret = spi_sync(st->spi, &st->msg);
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if (ret) {
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dev_err(&spi->dev, "device init failed\n");
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goto error_unprepare_mclk;
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}
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ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
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if (ret)
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goto error_unprepare_mclk;
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ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
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if (ret)
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goto error_unprepare_mclk;
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ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
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if (ret)
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goto error_unprepare_mclk;
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ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
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if (ret)
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goto error_unprepare_mclk;
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ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
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if (ret)
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goto error_unprepare_mclk;
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ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
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if (ret)
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goto error_unprepare_mclk;
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ret = iio_device_register(indio_dev);
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if (ret)
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goto error_unprepare_mclk;
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return 0;
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error_unprepare_mclk:
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clk_disable_unprepare(st->mclk);
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error_disable_dvdd:
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regulator_disable(st->dvdd);
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error_disable_avdd:
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regulator_disable(st->avdd);
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return ret;
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}
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static int ad9832_remove(struct spi_device *spi)
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{
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struct iio_dev *indio_dev = spi_get_drvdata(spi);
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struct ad9832_state *st = iio_priv(indio_dev);
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iio_device_unregister(indio_dev);
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clk_disable_unprepare(st->mclk);
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regulator_disable(st->dvdd);
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regulator_disable(st->avdd);
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return 0;
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}
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static const struct spi_device_id ad9832_id[] = {
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{"ad9832", 0},
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{"ad9835", 0},
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{}
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};
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MODULE_DEVICE_TABLE(spi, ad9832_id);
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static struct spi_driver ad9832_driver = {
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.driver = {
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.name = "ad9832",
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},
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.probe = ad9832_probe,
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.remove = ad9832_remove,
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.id_table = ad9832_id,
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};
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module_spi_driver(ad9832_driver);
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MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
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MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
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MODULE_LICENSE("GPL v2");
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