// SPDX-License-Identifier: GPL-2.0+
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/fs.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/firmware.h>
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#include <linux/io.h>
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#include "io.h"
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static inline void byte0_out(unsigned char data);
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static inline void byte1_out(unsigned char data);
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static inline void xl_cclk_b(int32_t i);
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/* Assert and Deassert CCLK */
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void xl_shift_cclk(int count)
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{
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int i;
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for (i = 0; i < count; i++) {
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xl_cclk_b(1);
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xl_cclk_b(0);
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}
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}
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int xl_supported_prog_bus_width(enum wbus bus_bytes)
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{
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switch (bus_bytes) {
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case bus_1byte:
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break;
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case bus_2byte:
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break;
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default:
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pr_err("unsupported program bus width %d\n", bus_bytes);
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return 0;
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}
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return 1;
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}
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/* Serialize byte and clock each bit on target's DIN and CCLK pins */
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void xl_shift_bytes_out(enum wbus bus_byte, unsigned char *pdata)
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{
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/*
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* supports 1 and 2 bytes programming mode
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*/
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if (likely(bus_byte == bus_2byte))
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byte0_out(pdata[0]);
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byte1_out(pdata[1]);
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xl_shift_cclk(1);
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}
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/*
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* generic bit swap for xilinx SYSTEMMAP FPGA programming
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*/
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void xl_program_b(int32_t i)
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{
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}
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void xl_rdwr_b(int32_t i)
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{
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}
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void xl_csi_b(int32_t i)
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{
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}
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int xl_get_init_b(void)
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{
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return -1;
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}
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int xl_get_done_b(void)
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{
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return -1;
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}
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static inline void byte0_out(unsigned char data)
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{
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}
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static inline void byte1_out(unsigned char data)
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{
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}
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static inline void xl_cclk_b(int32_t i)
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{
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}
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/*
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* configurable per device type for different I/O config
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*/
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int xl_init_io(void)
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{
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return -1;
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}
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