// SPDX-License-Identifier: GPL-2.0+
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/device.h>
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#include <linux/string.h>
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#include <linux/slab.h>
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#include <linux/fs.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/firmware.h>
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#include <asm/unaligned.h>
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#include "gs_fpgaboot.h"
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#include "io.h"
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#define DEVICE_NAME "device"
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#define CLASS_NAME "fpgaboot"
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static u8 bits_magic[] = {
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0x0, 0x9, 0xf, 0xf0, 0xf, 0xf0,
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0xf, 0xf0, 0xf, 0xf0, 0x0, 0x0, 0x1};
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/* fake device for request_firmware */
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static struct platform_device *firmware_pdev;
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static char *file = "xlinx_fpga_firmware.bit";
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module_param(file, charp, 0444);
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MODULE_PARM_DESC(file, "Xilinx FPGA firmware file.");
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static void read_bitstream(u8 *bitdata, u8 *buf, int *offset, int rdsize)
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{
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memcpy(buf, bitdata + *offset, rdsize);
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*offset += rdsize;
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}
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static int readinfo_bitstream(u8 *bitdata, u8 *buf, int size, int *offset)
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{
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u8 tbuf[2];
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u16 len;
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/* read section char */
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read_bitstream(bitdata, tbuf, offset, 1);
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/* read length */
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read_bitstream(bitdata, tbuf, offset, 2);
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len = get_unaligned_be16(tbuf);
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if (len >= size) {
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pr_err("error: readinfo buffer too small\n");
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return -EINVAL;
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}
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read_bitstream(bitdata, buf, offset, len);
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buf[len] = '\0';
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return 0;
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}
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/*
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* read bitdata length
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*/
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static int readlength_bitstream(u8 *bitdata, int *lendata, int *offset)
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{
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u8 tbuf[4];
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/* read section char */
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read_bitstream(bitdata, tbuf, offset, 1);
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/* make sure it is section 'e' */
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if (tbuf[0] != 'e') {
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pr_err("error: length section is not 'e', but %c\n", tbuf[0]);
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return -EINVAL;
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}
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/* read 4bytes length */
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read_bitstream(bitdata, tbuf, offset, 4);
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*lendata = get_unaligned_be32(tbuf);
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return 0;
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}
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/*
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* read first 13 bytes to check bitstream magic number
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*/
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static int readmagic_bitstream(u8 *bitdata, int *offset)
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{
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u8 buf[13];
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int r;
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read_bitstream(bitdata, buf, offset, 13);
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r = memcmp(buf, bits_magic, 13);
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if (r) {
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pr_err("error: corrupted header\n");
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return -EINVAL;
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}
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pr_info("bitstream file magic number Ok\n");
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*offset = 13; /* magic length */
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return 0;
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}
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/*
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* NOTE: supports only bitstream format
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*/
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static enum fmt_image get_imageformat(void)
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{
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return f_bit;
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}
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static void gs_print_header(struct fpgaimage *fimage)
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{
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pr_info("file: %s\n", fimage->filename);
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pr_info("part: %s\n", fimage->part);
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pr_info("date: %s\n", fimage->date);
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pr_info("time: %s\n", fimage->time);
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pr_info("lendata: %d\n", fimage->lendata);
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}
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static int gs_read_bitstream(struct fpgaimage *fimage)
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{
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u8 *bitdata;
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int offset;
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int err;
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offset = 0;
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bitdata = (u8 *)fimage->fw_entry->data;
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err = readmagic_bitstream(bitdata, &offset);
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if (err)
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return err;
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err = readinfo_bitstream(bitdata, fimage->filename, MAX_STR, &offset);
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if (err)
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return err;
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err = readinfo_bitstream(bitdata, fimage->part, MAX_STR, &offset);
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if (err)
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return err;
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err = readinfo_bitstream(bitdata, fimage->date, MAX_STR, &offset);
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if (err)
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return err;
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err = readinfo_bitstream(bitdata, fimage->time, MAX_STR, &offset);
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if (err)
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return err;
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err = readlength_bitstream(bitdata, &fimage->lendata, &offset);
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if (err)
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return err;
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fimage->fpgadata = bitdata + offset;
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return 0;
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}
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static int gs_read_image(struct fpgaimage *fimage)
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{
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int img_fmt;
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int err;
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img_fmt = get_imageformat();
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switch (img_fmt) {
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case f_bit:
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pr_info("image is bitstream format\n");
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err = gs_read_bitstream(fimage);
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if (err)
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return err;
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break;
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default:
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pr_err("unsupported fpga image format\n");
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return -EINVAL;
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}
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gs_print_header(fimage);
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return 0;
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}
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static int gs_load_image(struct fpgaimage *fimage, char *fw_file)
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{
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int err;
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pr_info("load fpgaimage %s\n", fw_file);
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err = request_firmware(&fimage->fw_entry, fw_file, &firmware_pdev->dev);
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if (err != 0) {
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pr_err("firmware %s is missing, cannot continue.\n", fw_file);
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return err;
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}
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return 0;
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}
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static int gs_download_image(struct fpgaimage *fimage, enum wbus bus_bytes)
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{
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u8 *bitdata;
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int size, i, cnt;
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cnt = 0;
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bitdata = (u8 *)fimage->fpgadata;
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size = fimage->lendata;
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#ifdef DEBUG_FPGA
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print_hex_dump_bytes("bitfile sample: ", DUMP_PREFIX_OFFSET,
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bitdata, 0x100);
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#endif /* DEBUG_FPGA */
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if (!xl_supported_prog_bus_width(bus_bytes)) {
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pr_err("unsupported program bus width %d\n",
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bus_bytes);
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return -EINVAL;
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}
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/* Bring csi_b, rdwr_b Low and program_b High */
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xl_program_b(1);
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xl_rdwr_b(0);
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xl_csi_b(0);
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/* Configuration reset */
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xl_program_b(0);
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msleep(20);
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xl_program_b(1);
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/* Wait for Device Initialization */
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while (xl_get_init_b() == 0)
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;
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pr_info("device init done\n");
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for (i = 0; i < size; i += bus_bytes)
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xl_shift_bytes_out(bus_bytes, bitdata + i);
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pr_info("program done\n");
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/* Check INIT_B */
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if (xl_get_init_b() == 0) {
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pr_err("init_b 0\n");
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return -EIO;
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}
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while (xl_get_done_b() == 0) {
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if (cnt++ > MAX_WAIT_DONE) {
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pr_err("init_B %d\n", xl_get_init_b());
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break;
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}
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}
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if (cnt > MAX_WAIT_DONE) {
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pr_err("fpga download fail\n");
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return -EIO;
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}
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pr_info("download fpgaimage\n");
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/* Compensate for Special Startup Conditions */
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xl_shift_cclk(8);
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return 0;
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}
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static int gs_release_image(struct fpgaimage *fimage)
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{
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release_firmware(fimage->fw_entry);
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pr_info("release fpgaimage\n");
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return 0;
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}
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/*
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* NOTE: supports systemmap parallel programming
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*/
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static int gs_set_download_method(struct fpgaimage *fimage)
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{
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pr_info("set program method\n");
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fimage->dmethod = m_systemmap;
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pr_info("systemmap program method\n");
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return 0;
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}
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static int init_driver(void)
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{
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firmware_pdev = platform_device_register_simple("fpgaboot", -1,
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NULL, 0);
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return PTR_ERR_OR_ZERO(firmware_pdev);
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}
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static int gs_fpgaboot(void)
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{
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int err;
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struct fpgaimage *fimage;
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fimage = kmalloc(sizeof(*fimage), GFP_KERNEL);
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if (!fimage)
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return -ENOMEM;
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err = gs_load_image(fimage, file);
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if (err) {
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pr_err("gs_load_image error\n");
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goto err_out1;
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}
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err = gs_read_image(fimage);
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if (err) {
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pr_err("gs_read_image error\n");
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goto err_out2;
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}
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err = gs_set_download_method(fimage);
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if (err) {
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pr_err("gs_set_download_method error\n");
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goto err_out2;
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}
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err = gs_download_image(fimage, bus_2byte);
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if (err) {
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pr_err("gs_download_image error\n");
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goto err_out2;
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}
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err = gs_release_image(fimage);
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if (err) {
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pr_err("gs_release_image error\n");
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goto err_out1;
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}
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kfree(fimage);
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return 0;
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err_out2:
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err = gs_release_image(fimage);
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if (err)
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pr_err("gs_release_image error\n");
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err_out1:
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kfree(fimage);
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return err;
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}
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static int __init gs_fpgaboot_init(void)
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{
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int err;
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pr_info("FPGA DOWNLOAD --->\n");
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pr_info("FPGA image file name: %s\n", file);
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err = init_driver();
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if (err) {
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pr_err("FPGA DRIVER INIT FAIL!!\n");
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return err;
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}
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err = xl_init_io();
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if (err) {
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pr_err("GPIO INIT FAIL!!\n");
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goto errout;
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}
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err = gs_fpgaboot();
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if (err) {
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pr_err("FPGA DOWNLOAD FAIL!!\n");
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goto errout;
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}
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pr_info("FPGA DOWNLOAD DONE <---\n");
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return 0;
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errout:
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platform_device_unregister(firmware_pdev);
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return err;
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}
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static void __exit gs_fpgaboot_exit(void)
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{
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platform_device_unregister(firmware_pdev);
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pr_info("FPGA image download module removed\n");
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}
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module_init(gs_fpgaboot_init);
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module_exit(gs_fpgaboot_exit);
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MODULE_AUTHOR("Insop Song");
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MODULE_DESCRIPTION("Xlinix FPGA firmware download");
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MODULE_LICENSE("GPL");
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