/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* DMA-able FIFO interface
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*
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* Copyright (C) 2012 Peter Hurley <peter@hurleysoftware.com>
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*/
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#ifndef _DMA_FIFO_H_
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#define _DMA_FIFO_H_
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/**
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* The design basis for the DMA FIFO is to provide an output side that
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* complies with the streaming DMA API design that can be DMA'd from directly
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* (without additional copying), coupled with an input side that maintains a
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* logically consistent 'apparent' size (ie, bytes in + bytes avail is static
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* for the lifetime of the FIFO).
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*
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* DMA output transactions originate on a cache line boundary and can be
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* variably-sized. DMA output transactions can be retired out-of-order but
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* the FIFO will only advance the output in the original input sequence.
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* This means the FIFO will eventually stall if a transaction is never retired.
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*
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* Chunking the output side into cache line multiples means that some FIFO
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* memory is unused. For example, if all the avail input has been pended out,
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* then the in and out markers are re-aligned to the next cache line.
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* The maximum possible waste is
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* (cache line alignment - 1) * (max outstanding dma transactions)
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* This potential waste requires additional hidden capacity within the FIFO
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* to be able to accept input while the 'apparent' size has not been reached.
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*
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* Additional cache lines (ie, guard area) are used to minimize DMA
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* fragmentation when wrapping at the end of the FIFO. Input is allowed into the
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* guard area, but the in and out FIFO markers are wrapped when DMA is pended.
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*/
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#define DMA_FIFO_GUARD 3 /* # of cache lines to reserve for the guard area */
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struct dma_fifo {
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unsigned int in;
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unsigned int out; /* updated when dma is pended */
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unsigned int done; /* updated upon dma completion */
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struct {
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unsigned corrupt:1;
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};
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int size; /* 'apparent' size of fifo */
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int guard; /* ofs of guard area */
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int capacity; /* size + reserved */
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int avail; /* # of unused bytes in fifo */
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unsigned int align; /* must be power of 2 */
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int tx_limit; /* max # of bytes per dma transaction */
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int open_limit; /* max # of outstanding allowed */
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int open; /* # of outstanding dma transactions */
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struct list_head pending; /* fifo markers for outstanding dma */
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void *data;
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};
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struct dma_pending {
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struct list_head link;
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void *data;
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unsigned int len;
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unsigned int next;
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unsigned int out;
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};
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static inline void dp_mark_completed(struct dma_pending *dp)
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{
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dp->data += 1;
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}
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static inline bool dp_is_completed(struct dma_pending *dp)
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{
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return (unsigned long)dp->data & 1UL;
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}
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void dma_fifo_init(struct dma_fifo *fifo);
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int dma_fifo_alloc(struct dma_fifo *fifo, int size, unsigned int align,
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int tx_limit, int open_limit, gfp_t gfp_mask);
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void dma_fifo_free(struct dma_fifo *fifo);
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void dma_fifo_reset(struct dma_fifo *fifo);
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int dma_fifo_in(struct dma_fifo *fifo, const void *src, int n);
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int dma_fifo_out_pend(struct dma_fifo *fifo, struct dma_pending *pended);
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int dma_fifo_out_complete(struct dma_fifo *fifo,
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struct dma_pending *complete);
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/* returns the # of used bytes in the fifo */
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static inline int dma_fifo_level(struct dma_fifo *fifo)
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{
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return fifo->size - fifo->avail;
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}
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/* returns the # of bytes ready for output in the fifo */
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static inline int dma_fifo_out_level(struct dma_fifo *fifo)
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{
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return fifo->in - fifo->out;
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}
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/* returns the # of unused bytes in the fifo */
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static inline int dma_fifo_avail(struct dma_fifo *fifo)
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{
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return fifo->avail;
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}
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/* returns true if fifo has max # of outstanding dmas */
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static inline bool dma_fifo_busy(struct dma_fifo *fifo)
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{
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return fifo->open == fifo->open_limit;
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}
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/* changes the max size of dma returned from dma_fifo_out_pend() */
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static inline int dma_fifo_change_tx_limit(struct dma_fifo *fifo, int tx_limit)
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{
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tx_limit = round_down(tx_limit, fifo->align);
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fifo->tx_limit = max_t(int, tx_limit, fifo->align);
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return 0;
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}
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#endif /* _DMA_FIFO_H_ */
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