/*
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* Allwinner H5 SoC pinctrl driver.
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*
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* Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
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*
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* Based on pinctrl-sun8i-h3.c, which is:
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* Based on pinctrl-sun8i-a23.c, which is:
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* Copyright (C) 2014 Chen-Yu Tsai <wens@csie.org>
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* Copyright (C) 2014 Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/pinctrl/pinctrl.h>
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#include "pinctrl-sunxi.h"
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static const struct sunxi_desc_pin sun50i_h5_pins[] = {
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* TX */
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SUNXI_FUNCTION(0x3, "jtag"), /* MS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* RX */
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SUNXI_FUNCTION(0x3, "jtag"), /* CK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
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SUNXI_FUNCTION(0x3, "jtag"), /* DO */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
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SUNXI_FUNCTION(0x3, "jtag"), /* DI */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart0"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "uart0"), /* RX */
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SUNXI_FUNCTION(0x3, "pwm0"),
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "sim"), /* PWREN */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "sim"), /* CLK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "sim"), /* DATA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "sim"), /* RST */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "sim"), /* DET */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
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SUNXI_FUNCTION(0x3, "di"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
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SUNXI_FUNCTION(0x3, "di"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi1"), /* CS */
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SUNXI_FUNCTION(0x3, "uart3"), /* TX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
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SUNXI_FUNCTION(0x3, "uart3"), /* RX */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
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SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
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SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
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SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
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SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
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SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
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SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */
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SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
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/* Hole */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* WE */
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SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
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SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
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SUNXI_FUNCTION(0x4, "mmc2")), /* DS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
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SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
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SUNXI_FUNCTION(0x3, "spi0")), /* CS */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
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SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* RE */
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SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
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SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
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SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
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SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
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SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
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SUNXI_FUNCTION(0x0, "gpio_in"),
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SUNXI_FUNCTION(0x1, "gpio_out"),
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SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
|
SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
|
SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */
|
SUNXI_FUNCTION(0x3, "di"), /* TX */
|
SUNXI_FUNCTION(0x4, "ts2")), /* CLK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */
|
SUNXI_FUNCTION(0x3, "di"), /* RX */
|
SUNXI_FUNCTION(0x4, "ts2")), /* ERR */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */
|
SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */
|
SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* RXCK */
|
SUNXI_FUNCTION(0x4, "ts2")), /* D0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */
|
SUNXI_FUNCTION(0x4, "ts2")), /* D1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* RXERR */
|
SUNXI_FUNCTION(0x4, "ts2")), /* D2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */
|
SUNXI_FUNCTION(0x4, "ts2"), /* D3 */
|
SUNXI_FUNCTION(0x5, "ts3")), /* CLK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */
|
SUNXI_FUNCTION(0x4, "ts2"), /* D4 */
|
SUNXI_FUNCTION(0x5, "ts3")), /* ERR */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */
|
SUNXI_FUNCTION(0x4, "ts2"), /* D5 */
|
SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */
|
SUNXI_FUNCTION(0x4, "ts2"), /* D6 */
|
SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* CRS */
|
SUNXI_FUNCTION(0x4, "ts2"), /* D7 */
|
SUNXI_FUNCTION(0x5, "ts3")), /* D0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* TXCK */
|
SUNXI_FUNCTION(0x4, "sim")), /* PWREN */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */
|
SUNXI_FUNCTION(0x4, "sim")), /* CLK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* TXERR */
|
SUNXI_FUNCTION(0x4, "sim")), /* DATA */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */
|
SUNXI_FUNCTION(0x4, "sim")), /* RST */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac"), /* MDC */
|
SUNXI_FUNCTION(0x4, "sim")), /* DET */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "emac")), /* MDIO */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
|
SUNXI_FUNCTION(0x3, "ts0")), /* CLK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
|
SUNXI_FUNCTION(0x3, "ts0")), /* ERR */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
|
SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
|
SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D0 */
|
SUNXI_FUNCTION(0x3, "ts0")), /* D0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D1 */
|
SUNXI_FUNCTION(0x3, "ts0")), /* D1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D2 */
|
SUNXI_FUNCTION(0x3, "ts0")), /* D2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D3 */
|
SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
|
SUNXI_FUNCTION(0x4, "ts1")), /* CLK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D4 */
|
SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
|
SUNXI_FUNCTION(0x4, "ts1")), /* ERR */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D5 */
|
SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
|
SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D6 */
|
SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
|
SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* D7 */
|
SUNXI_FUNCTION(0x3, "ts"), /* D7 */
|
SUNXI_FUNCTION(0x4, "ts1")), /* D0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* SCK */
|
SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "csi"), /* SDA */
|
SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
|
SUNXI_FUNCTION(0x3, "jtag"), /* MS */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PF_EINT0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
|
SUNXI_FUNCTION(0x3, "jtag"), /* DI */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PF_EINT1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
|
SUNXI_FUNCTION(0x3, "uart0"), /* TX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PF_EINT2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
|
SUNXI_FUNCTION(0x3, "jtag"), /* DO */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PF_EINT3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
|
SUNXI_FUNCTION(0x3, "uart0"), /* RX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PF_EINT4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
|
SUNXI_FUNCTION(0x3, "jtag"), /* CK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PF_EINT5 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PF_EINT6 */
|
/* Hole */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 0)), /* PG_EINT0 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 1)), /* PG_EINT1 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 2)), /* PG_EINT2 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 3)), /* PG_EINT3 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 4)), /* PG_EINT4 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 5)), /* PG_EINT5 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /* TX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 6)), /* PG_EINT6 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /* RX */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 7)), /* PG_EINT7 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 8)), /* PG_EINT8 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 9)), /* PG_EINT9 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 10)), /* PG_EINT10 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 11)), /* PG_EINT11 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 12)), /* PG_EINT12 */
|
SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
|
SUNXI_FUNCTION(0x0, "gpio_in"),
|
SUNXI_FUNCTION(0x1, "gpio_out"),
|
SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
|
SUNXI_FUNCTION_IRQ_BANK(0x6, 2, 13)), /* PG_EINT13 */
|
};
|
|
static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data_broken = {
|
.pins = sun50i_h5_pins,
|
.npins = ARRAY_SIZE(sun50i_h5_pins),
|
.irq_banks = 2,
|
.irq_read_needs_mux = true,
|
.disable_strict_mode = true,
|
};
|
|
static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
|
.pins = sun50i_h5_pins,
|
.npins = ARRAY_SIZE(sun50i_h5_pins),
|
.irq_banks = 3,
|
.irq_read_needs_mux = true,
|
.disable_strict_mode = true,
|
};
|
|
static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
|
{
|
int ret;
|
|
ret = platform_irq_count(pdev);
|
if (ret < 0) {
|
if (ret != -EPROBE_DEFER)
|
dev_err(&pdev->dev, "Couldn't determine irq count: %pe\n",
|
ERR_PTR(ret));
|
return ret;
|
}
|
|
switch (ret) {
|
case 2:
|
dev_warn(&pdev->dev,
|
"Your device tree's pinctrl node is broken, which has no IRQ of PG bank routed.\n");
|
dev_warn(&pdev->dev,
|
"Please update the device tree, otherwise PG bank IRQ won't work.\n");
|
return sunxi_pinctrl_init(pdev,
|
&sun50i_h5_pinctrl_data_broken);
|
case 3:
|
return sunxi_pinctrl_init(pdev,
|
&sun50i_h5_pinctrl_data);
|
default:
|
return -EINVAL;
|
}
|
}
|
|
static const struct of_device_id sun50i_h5_pinctrl_match[] = {
|
{ .compatible = "allwinner,sun50i-h5-pinctrl", },
|
{}
|
};
|
|
static struct platform_driver sun50i_h5_pinctrl_driver = {
|
.probe = sun50i_h5_pinctrl_probe,
|
.driver = {
|
.name = "sun50i-h5-pinctrl",
|
.of_match_table = sun50i_h5_pinctrl_match,
|
},
|
};
|
builtin_platform_driver(sun50i_h5_pinctrl_driver);
|
