/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (C) 2016 IBM Corp.
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*/
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#ifndef PINCTRL_ASPEED
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#define PINCTRL_ASPEED
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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#include <linux/pinctrl/pinconf.h>
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#include <linux/pinctrl/pinconf-generic.h>
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#include <linux/regmap.h>
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#include "pinmux-aspeed.h"
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/**
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* @param The pinconf parameter type
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* @pins The pin range this config struct covers, [low, high]
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* @reg The register housing the configuration bits
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* @mask The mask to select the bits of interest in @reg
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*/
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struct aspeed_pin_config {
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enum pin_config_param param;
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unsigned int pins[2];
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unsigned int reg;
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u32 mask;
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};
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#define ASPEED_PINCTRL_PIN(name_) \
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[name_] = { \
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.number = name_, \
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.name = #name_, \
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.drv_data = (void *) &(PIN_SYM(name_)) \
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}
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#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \
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.param = param_, \
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.pins = {pin0_, pin1_}, \
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.reg = reg_, \
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.mask = BIT_MASK(bit_) \
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}
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#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \
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ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \
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ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
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#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \
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ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \
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ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_)
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/*
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* Aspeed pin configuration description.
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*
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* @param: pinconf configuration parameter
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* @arg: The supported argument for @param, or -1 if any value is supported
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* @val: The register value to write to configure @arg for @param
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* @mask: The bitfield mask for @val
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*
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* The map is to be used in conjunction with the configuration array supplied
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* by the driver implementation.
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*/
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struct aspeed_pin_config_map {
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enum pin_config_param param;
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s32 arg;
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u32 val;
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u32 mask;
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};
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struct aspeed_pinctrl_data {
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struct regmap *scu;
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const struct pinctrl_pin_desc *pins;
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const unsigned int npins;
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const struct aspeed_pin_config *configs;
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const unsigned int nconfigs;
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struct aspeed_pinmux_data pinmux;
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const struct aspeed_pin_config_map *confmaps;
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const unsigned int nconfmaps;
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};
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/* Aspeed pinctrl helpers */
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int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev);
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const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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unsigned int group);
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int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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unsigned int group, const unsigned int **pins,
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unsigned int *npins);
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void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
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struct seq_file *s, unsigned int offset);
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int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev);
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const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev,
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unsigned int function);
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int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
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unsigned int function, const char * const **groups,
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unsigned int * const num_groups);
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int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
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unsigned int group);
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int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
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struct pinctrl_gpio_range *range,
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unsigned int offset);
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int aspeed_pinctrl_probe(struct platform_device *pdev,
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struct pinctrl_desc *pdesc,
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struct aspeed_pinctrl_data *pdata);
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int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset,
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unsigned long *config);
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int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
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unsigned long *configs, unsigned int num_configs);
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int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev,
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unsigned int selector,
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unsigned long *config);
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int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev,
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unsigned int selector,
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unsigned long *configs,
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unsigned int num_configs);
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#endif /* PINCTRL_ASPEED */
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