/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/* Copyright(c) 2018-2019 Realtek Corporation
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*/
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#ifndef __RTW_RX_H_
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#define __RTW_RX_H_
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enum rtw_rx_desc_enc {
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RX_DESC_ENC_NONE = 0,
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RX_DESC_ENC_WEP40 = 1,
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RX_DESC_ENC_TKIP_WO_MIC = 2,
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RX_DESC_ENC_TKIP_MIC = 3,
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RX_DESC_ENC_AES = 4,
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RX_DESC_ENC_WEP104 = 5,
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};
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#define GET_RX_DESC_PHYST(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(26))
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#define GET_RX_DESC_ICV_ERR(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(15))
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#define GET_RX_DESC_CRC32(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(14))
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#define GET_RX_DESC_SWDEC(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x00), BIT(27))
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#define GET_RX_DESC_C2H(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x02), BIT(28))
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#define GET_RX_DESC_PKT_LEN(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(13, 0))
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#define GET_RX_DESC_DRV_INFO_SIZE(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(19, 16))
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#define GET_RX_DESC_SHIFT(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(25, 24))
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#define GET_RX_DESC_ENC_TYPE(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x00), GENMASK(22, 20))
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#define GET_RX_DESC_RX_RATE(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x03), GENMASK(6, 0))
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#define GET_RX_DESC_MACID(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x01), GENMASK(6, 0))
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#define GET_RX_DESC_PPDU_CNT(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x02), GENMASK(30, 29))
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#define GET_RX_DESC_TSFL(rxdesc) \
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le32_get_bits(*((__le32 *)(rxdesc) + 0x05), GENMASK(31, 0))
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void rtw_rx_stats(struct rtw_dev *rtwdev, struct ieee80211_vif *vif,
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struct sk_buff *skb);
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void rtw_rx_fill_rx_status(struct rtw_dev *rtwdev,
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struct rtw_rx_pkt_stat *pkt_stat,
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struct ieee80211_hdr *hdr,
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struct ieee80211_rx_status *rx_status,
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u8 *phy_status);
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#endif
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