/*
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* Shared Atheros AR9170 Header
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*
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* RX/TX meta descriptor format
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*
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* Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
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* Copyright 2009-2011 Christian Lamparter <chunkeey@googlemail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, see
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* http://www.gnu.org/licenses/.
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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* Copyright (c) 2007-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef __CARL9170_SHARED_WLAN_H
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#define __CARL9170_SHARED_WLAN_H
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#include "fwcmd.h"
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#define AR9170_RX_PHY_RATE_CCK_1M 0x0a
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#define AR9170_RX_PHY_RATE_CCK_2M 0x14
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#define AR9170_RX_PHY_RATE_CCK_5M 0x37
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#define AR9170_RX_PHY_RATE_CCK_11M 0x6e
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#define AR9170_ENC_ALG_NONE 0x0
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#define AR9170_ENC_ALG_WEP64 0x1
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#define AR9170_ENC_ALG_TKIP 0x2
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#define AR9170_ENC_ALG_AESCCMP 0x4
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#define AR9170_ENC_ALG_WEP128 0x5
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#define AR9170_ENC_ALG_WEP256 0x6
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#define AR9170_ENC_ALG_CENC 0x7
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#define AR9170_RX_ENC_SOFTWARE 0x8
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#define AR9170_RX_STATUS_MODULATION 0x03
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#define AR9170_RX_STATUS_MODULATION_S 0
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#define AR9170_RX_STATUS_MODULATION_CCK 0x00
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#define AR9170_RX_STATUS_MODULATION_OFDM 0x01
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#define AR9170_RX_STATUS_MODULATION_HT 0x02
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#define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
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/* depends on modulation */
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#define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
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#define AR9170_RX_STATUS_GREENFIELD 0x08
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#define AR9170_RX_STATUS_MPDU 0x30
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#define AR9170_RX_STATUS_MPDU_S 4
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#define AR9170_RX_STATUS_MPDU_SINGLE 0x00
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#define AR9170_RX_STATUS_MPDU_FIRST 0x20
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#define AR9170_RX_STATUS_MPDU_MIDDLE 0x30
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#define AR9170_RX_STATUS_MPDU_LAST 0x10
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#define AR9170_RX_STATUS_CONT_AGGR 0x40
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#define AR9170_RX_STATUS_TOTAL_ERROR 0x80
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#define AR9170_RX_ERROR_RXTO 0x01
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#define AR9170_RX_ERROR_OVERRUN 0x02
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#define AR9170_RX_ERROR_DECRYPT 0x04
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#define AR9170_RX_ERROR_FCS 0x08
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#define AR9170_RX_ERROR_WRONG_RA 0x10
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#define AR9170_RX_ERROR_PLCP 0x20
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#define AR9170_RX_ERROR_MMIC 0x40
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/* these are either-or */
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#define AR9170_TX_MAC_PROT_RTS 0x0001
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#define AR9170_TX_MAC_PROT_CTS 0x0002
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#define AR9170_TX_MAC_PROT 0x0003
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#define AR9170_TX_MAC_NO_ACK 0x0004
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/* if unset, MAC will only do SIFS space before frame */
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#define AR9170_TX_MAC_BACKOFF 0x0008
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#define AR9170_TX_MAC_BURST 0x0010
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#define AR9170_TX_MAC_AGGR 0x0020
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/* encryption is a two-bit field */
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#define AR9170_TX_MAC_ENCR_NONE 0x0000
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#define AR9170_TX_MAC_ENCR_RC4 0x0040
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#define AR9170_TX_MAC_ENCR_CENC 0x0080
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#define AR9170_TX_MAC_ENCR_AES 0x00c0
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#define AR9170_TX_MAC_MMIC 0x0100
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#define AR9170_TX_MAC_HW_DURATION 0x0200
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#define AR9170_TX_MAC_QOS_S 10
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#define AR9170_TX_MAC_QOS 0x0c00
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#define AR9170_TX_MAC_DISABLE_TXOP 0x1000
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#define AR9170_TX_MAC_TXOP_RIFS 0x2000
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#define AR9170_TX_MAC_IMM_BA 0x4000
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/* either-or */
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#define AR9170_TX_PHY_MOD_CCK 0x00000000
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#define AR9170_TX_PHY_MOD_OFDM 0x00000001
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#define AR9170_TX_PHY_MOD_HT 0x00000002
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/* depends on modulation */
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#define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
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#define AR9170_TX_PHY_GREENFIELD 0x00000004
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#define AR9170_TX_PHY_BW_S 3
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#define AR9170_TX_PHY_BW (3 << AR9170_TX_PHY_BW_SHIFT)
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#define AR9170_TX_PHY_BW_20MHZ 0
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#define AR9170_TX_PHY_BW_40MHZ 2
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#define AR9170_TX_PHY_BW_40MHZ_DUP 3
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#define AR9170_TX_PHY_TX_HEAVY_CLIP_S 6
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#define AR9170_TX_PHY_TX_HEAVY_CLIP (7 << \
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AR9170_TX_PHY_TX_HEAVY_CLIP_S)
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#define AR9170_TX_PHY_TX_PWR_S 9
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#define AR9170_TX_PHY_TX_PWR (0x3f << \
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AR9170_TX_PHY_TX_PWR_S)
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#define AR9170_TX_PHY_TXCHAIN_S 15
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#define AR9170_TX_PHY_TXCHAIN (7 << \
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AR9170_TX_PHY_TXCHAIN_S)
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#define AR9170_TX_PHY_TXCHAIN_1 1
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/* use for cck, ofdm 6/9/12/18/24 and HT if capable */
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#define AR9170_TX_PHY_TXCHAIN_2 5
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#define AR9170_TX_PHY_MCS_S 18
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#define AR9170_TX_PHY_MCS (0x7f << \
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AR9170_TX_PHY_MCS_S)
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#define AR9170_TX_PHY_RATE_CCK_1M 0x0
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#define AR9170_TX_PHY_RATE_CCK_2M 0x1
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#define AR9170_TX_PHY_RATE_CCK_5M 0x2
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#define AR9170_TX_PHY_RATE_CCK_11M 0x3
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/* same as AR9170_RX_PHY_RATE */
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#define AR9170_TXRX_PHY_RATE_OFDM_6M 0xb
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#define AR9170_TXRX_PHY_RATE_OFDM_9M 0xf
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#define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa
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#define AR9170_TXRX_PHY_RATE_OFDM_18M 0xe
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#define AR9170_TXRX_PHY_RATE_OFDM_24M 0x9
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#define AR9170_TXRX_PHY_RATE_OFDM_36M 0xd
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#define AR9170_TXRX_PHY_RATE_OFDM_48M 0x8
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#define AR9170_TXRX_PHY_RATE_OFDM_54M 0xc
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#define AR9170_TXRX_PHY_RATE_HT_MCS0 0x0
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#define AR9170_TXRX_PHY_RATE_HT_MCS1 0x1
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#define AR9170_TXRX_PHY_RATE_HT_MCS2 0x2
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#define AR9170_TXRX_PHY_RATE_HT_MCS3 0x3
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#define AR9170_TXRX_PHY_RATE_HT_MCS4 0x4
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#define AR9170_TXRX_PHY_RATE_HT_MCS5 0x5
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#define AR9170_TXRX_PHY_RATE_HT_MCS6 0x6
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#define AR9170_TXRX_PHY_RATE_HT_MCS7 0x7
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#define AR9170_TXRX_PHY_RATE_HT_MCS8 0x8
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#define AR9170_TXRX_PHY_RATE_HT_MCS9 0x9
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#define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa
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#define AR9170_TXRX_PHY_RATE_HT_MCS11 0xb
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#define AR9170_TXRX_PHY_RATE_HT_MCS12 0xc
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#define AR9170_TXRX_PHY_RATE_HT_MCS13 0xd
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#define AR9170_TXRX_PHY_RATE_HT_MCS14 0xe
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#define AR9170_TXRX_PHY_RATE_HT_MCS15 0xf
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#define AR9170_TX_PHY_SHORT_GI 0x80000000
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#ifdef __CARL9170FW__
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struct ar9170_tx_hw_mac_control {
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union {
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struct {
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/*
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* Beware of compiler bugs in all gcc pre 4.4!
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*/
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u8 erp_prot:2;
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u8 no_ack:1;
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u8 backoff:1;
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u8 burst:1;
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u8 ampdu:1;
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u8 enc_mode:2;
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u8 hw_mmic:1;
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u8 hw_duration:1;
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u8 qos_queue:2;
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u8 disable_txop:1;
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u8 txop_rifs:1;
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u8 ba_end:1;
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u8 probe:1;
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} __packed;
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__le16 set;
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} __packed;
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} __packed;
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struct ar9170_tx_hw_phy_control {
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union {
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struct {
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/*
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* Beware of compiler bugs in all gcc pre 4.4!
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*/
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u8 modulation:2;
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u8 preamble:1;
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u8 bandwidth:2;
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u8:1;
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u8 heavy_clip:3;
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u8 tx_power:6;
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u8 chains:3;
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u8 mcs:7;
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u8:6;
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u8 short_gi:1;
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} __packed;
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__le32 set;
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} __packed;
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} __packed;
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struct ar9170_tx_rate_info {
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u8 tries:3;
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u8 erp_prot:2;
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u8 ampdu:1;
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u8 free:2; /* free for use (e.g.:RIFS/TXOP/AMPDU) */
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} __packed;
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struct carl9170_tx_superdesc {
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__le16 len;
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u8 rix;
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u8 cnt;
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u8 cookie;
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u8 ampdu_density:3;
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u8 ampdu_factor:2;
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u8 ampdu_commit_density:1;
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u8 ampdu_commit_factor:1;
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u8 ampdu_unused_bit:1;
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u8 queue:2;
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u8 assign_seq:1;
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u8 vif_id:3;
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u8 fill_in_tsf:1;
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u8 cab:1;
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u8 padding2;
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struct ar9170_tx_rate_info ri[CARL9170_TX_MAX_RATES];
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struct ar9170_tx_hw_phy_control rr[CARL9170_TX_MAX_RETRY_RATES];
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} __packed;
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struct ar9170_tx_hwdesc {
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__le16 length;
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struct ar9170_tx_hw_mac_control mac;
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struct ar9170_tx_hw_phy_control phy;
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} __packed;
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struct ar9170_tx_frame {
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struct ar9170_tx_hwdesc hdr;
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union {
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struct ieee80211_hdr i3e;
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u8 payload[0];
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} data;
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} __packed;
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struct carl9170_tx_superframe {
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struct carl9170_tx_superdesc s;
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struct ar9170_tx_frame f;
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} __packed __aligned(4);
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#endif /* __CARL9170FW__ */
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struct _ar9170_tx_hwdesc {
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__le16 length;
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__le16 mac_control;
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__le32 phy_control;
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} __packed;
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#define CARL9170_TX_SUPER_AMPDU_DENSITY_S 0
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#define CARL9170_TX_SUPER_AMPDU_DENSITY 0x7
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#define CARL9170_TX_SUPER_AMPDU_FACTOR 0x18
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#define CARL9170_TX_SUPER_AMPDU_FACTOR_S 3
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#define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY 0x20
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#define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY_S 5
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#define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40
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#define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR_S 6
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#define CARL9170_TX_SUPER_MISC_QUEUE 0x3
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#define CARL9170_TX_SUPER_MISC_QUEUE_S 0
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#define CARL9170_TX_SUPER_MISC_ASSIGN_SEQ 0x4
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#define CARL9170_TX_SUPER_MISC_VIF_ID 0x38
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#define CARL9170_TX_SUPER_MISC_VIF_ID_S 3
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#define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40
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#define CARL9170_TX_SUPER_MISC_CAB 0x80
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#define CARL9170_TX_SUPER_RI_TRIES 0x7
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#define CARL9170_TX_SUPER_RI_TRIES_S 0
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#define CARL9170_TX_SUPER_RI_ERP_PROT 0x18
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#define CARL9170_TX_SUPER_RI_ERP_PROT_S 3
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#define CARL9170_TX_SUPER_RI_AMPDU 0x20
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#define CARL9170_TX_SUPER_RI_AMPDU_S 5
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struct _carl9170_tx_superdesc {
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__le16 len;
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u8 rix;
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u8 cnt;
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u8 cookie;
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u8 ampdu_settings;
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u8 misc;
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u8 padding;
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u8 ri[CARL9170_TX_MAX_RATES];
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__le32 rr[CARL9170_TX_MAX_RETRY_RATES];
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} __packed;
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struct _carl9170_tx_superframe {
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struct _carl9170_tx_superdesc s;
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struct _ar9170_tx_hwdesc f;
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u8 frame_data[0];
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} __packed __aligned(4);
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#define CARL9170_TX_SUPERDESC_LEN 24
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#define AR9170_TX_HWDESC_LEN 8
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#define CARL9170_TX_SUPERFRAME_LEN (CARL9170_TX_SUPERDESC_LEN + \
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AR9170_TX_HWDESC_LEN)
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struct ar9170_rx_head {
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u8 plcp[12];
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} __packed;
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#define AR9170_RX_HEAD_LEN 12
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struct ar9170_rx_phystatus {
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union {
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struct {
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u8 rssi_ant0, rssi_ant1, rssi_ant2,
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rssi_ant0x, rssi_ant1x, rssi_ant2x,
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rssi_combined;
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} __packed;
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u8 rssi[7];
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} __packed;
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u8 evm_stream0[6], evm_stream1[6];
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u8 phy_err;
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} __packed;
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#define AR9170_RX_PHYSTATUS_LEN 20
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struct ar9170_rx_macstatus {
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u8 SAidx, DAidx;
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u8 error;
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u8 status;
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} __packed;
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#define AR9170_RX_MACSTATUS_LEN 4
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struct ar9170_rx_frame_single {
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struct ar9170_rx_head phy_head;
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struct ieee80211_hdr i3e;
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struct ar9170_rx_phystatus phy_tail;
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struct ar9170_rx_macstatus macstatus;
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} __packed;
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struct ar9170_rx_frame_head {
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struct ar9170_rx_head phy_head;
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struct ieee80211_hdr i3e;
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struct ar9170_rx_macstatus macstatus;
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} __packed;
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struct ar9170_rx_frame_middle {
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struct ieee80211_hdr i3e;
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struct ar9170_rx_macstatus macstatus;
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} __packed;
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struct ar9170_rx_frame_tail {
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struct ieee80211_hdr i3e;
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struct ar9170_rx_phystatus phy_tail;
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struct ar9170_rx_macstatus macstatus;
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} __packed;
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struct ar9170_rx_frame {
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union {
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struct ar9170_rx_frame_single single;
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struct ar9170_rx_frame_head head;
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struct ar9170_rx_frame_middle middle;
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struct ar9170_rx_frame_tail tail;
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} __packed;
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} __packed;
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static inline u8 ar9170_get_decrypt_type(struct ar9170_rx_macstatus *t)
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{
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return (t->SAidx & 0xc0) >> 4 |
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(t->DAidx & 0xc0) >> 6;
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}
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/*
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* This is an workaround for several undocumented bugs.
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* Don't mess with the QoS/AC <-> HW Queue map, if you don't
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* know what you are doing.
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*
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* Known problems [hardware]:
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* * The MAC does not aggregate frames on anything other
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* than the first HW queue.
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* * when an AMPDU is placed [in the first hw queue] and
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* additional frames are already queued on a different
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* hw queue, the MAC will ALWAYS freeze.
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*
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* In a nutshell: The hardware can either do QoS or
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* Aggregation but not both at the same time. As a
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* result, this makes the device pretty much useless
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* for any serious 802.11n setup.
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*/
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enum ar9170_txq {
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AR9170_TXQ_BK = 0, /* TXQ0 */
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AR9170_TXQ_BE, /* TXQ1 */
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AR9170_TXQ_VI, /* TXQ2 */
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AR9170_TXQ_VO, /* TXQ3 */
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__AR9170_NUM_TXQ,
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};
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#define AR9170_TXQ_DEPTH 32
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#endif /* __CARL9170_SHARED_WLAN_H */
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