/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell OcteonTx2 RVU Ethernet driver
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*
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* Copyright (C) 2020 Marvell International Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef OTX2_TXRX_H
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#define OTX2_TXRX_H
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#include <linux/etherdevice.h>
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#include <linux/iommu.h>
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#include <linux/if_vlan.h>
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#define LBK_CHAN_BASE 0x000
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#define SDP_CHAN_BASE 0x700
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#define CGX_CHAN_BASE 0x800
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#define OTX2_DATA_ALIGN(X) ALIGN(X, OTX2_ALIGN)
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#define OTX2_HEAD_ROOM OTX2_ALIGN
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#define OTX2_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN)
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#define OTX2_MIN_MTU 64
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#define OTX2_MAX_MTU (9212 - OTX2_ETH_HLEN)
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#define OTX2_MAX_GSO_SEGS 255
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#define OTX2_MAX_FRAGS_IN_SQE 9
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/* Rx buffer size should be in multiples of 128bytes */
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#define RCV_FRAG_LEN1(x) \
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((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
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OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
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/* Prefer 2048 byte buffers for better last level cache
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* utilization or data distribution across regions.
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*/
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#define RCV_FRAG_LEN(x) \
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((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
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#define DMA_BUFFER_LEN(x) \
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((x) - OTX2_HEAD_ROOM - \
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OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
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/* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
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* is equal to this value.
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*/
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#define CQ_CQE_THRESH_DEFAULT 10
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/* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
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* is nonzero and this much time elapses after that.
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*/
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#define CQ_TIMER_THRESH_DEFAULT 1 /* 1 usec */
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#define CQ_TIMER_THRESH_MAX 25 /* 25 usec */
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/* Min number of CQs (of the ones mapped to this CINT)
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* with valid CQEs.
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*/
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#define CQ_QCOUNT_DEFAULT 1
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struct queue_stats {
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u64 bytes;
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u64 pkts;
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};
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struct otx2_rcv_queue {
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struct queue_stats stats;
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};
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struct sg_list {
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u16 num_segs;
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u64 skb;
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u64 size[OTX2_MAX_FRAGS_IN_SQE];
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u64 dma_addr[OTX2_MAX_FRAGS_IN_SQE];
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};
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struct otx2_snd_queue {
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u8 aura_id;
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u16 head;
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u16 sqe_size;
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u32 sqe_cnt;
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u16 num_sqbs;
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u16 sqe_thresh;
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u8 sqe_per_sqb;
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u64 io_addr;
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u64 *aura_fc_addr;
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u64 *lmt_addr;
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void *sqe_base;
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struct qmem *sqe;
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struct qmem *tso_hdrs;
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struct sg_list *sg;
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struct qmem *timestamps;
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struct queue_stats stats;
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u16 sqb_count;
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u64 *sqb_ptrs;
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} ____cacheline_aligned_in_smp;
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enum cq_type {
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CQ_RX,
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CQ_TX,
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CQS_PER_CINT = 2, /* RQ + SQ */
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};
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struct otx2_cq_poll {
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void *dev;
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#define CINT_INVALID_CQ 255
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u8 cint_idx;
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u8 cq_ids[CQS_PER_CINT];
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struct napi_struct napi;
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};
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struct otx2_pool {
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struct qmem *stack;
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struct qmem *fc_addr;
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u16 rbsize;
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};
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struct otx2_cq_queue {
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u8 cq_idx;
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u8 cq_type;
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u8 cint_idx; /* CQ interrupt id */
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u8 refill_task_sched;
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u16 cqe_size;
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u16 pool_ptrs;
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u32 cqe_cnt;
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u32 cq_head;
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void *cqe_base;
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struct qmem *cqe;
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struct otx2_pool *rbpool;
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} ____cacheline_aligned_in_smp;
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struct otx2_qset {
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u32 rqe_cnt;
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u32 sqe_cnt; /* Keep these two at top */
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#define OTX2_MAX_CQ_CNT 64
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u16 cq_cnt;
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u16 xqe_size;
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struct otx2_pool *pool;
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struct otx2_cq_poll *napi;
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struct otx2_cq_queue *cq;
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struct otx2_snd_queue *sq;
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struct otx2_rcv_queue *rq;
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};
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/* Translate IOVA to physical address */
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static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
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{
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/* Translation is installed only when IOMMU is present */
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if (likely(iommu_domain))
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return iommu_iova_to_phys(iommu_domain, dma_addr);
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return dma_addr;
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}
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int otx2_napi_handler(struct napi_struct *napi, int budget);
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bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
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struct sk_buff *skb, u16 qidx);
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#endif /* OTX2_TXRX_H */
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